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A49LF040 Datasheet(PDF) 18 Page - AMIC Technology

Part No. A49LF040
Description  4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory
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Maker  AMICC [AMIC Technology]
Homepage  http://www.amictechnology.com
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A49LF040 Datasheet(HTML) 18 Page - AMIC Technology

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A49LF040
PRELIMINARY
(August, 2004, Version 0.1)
17
AMIC Technology, Corp.
Table 18: LPC Mode Interface AC Input/Output Characteristics
Symbol
Parameter
Test Conditions
Min
Max
Units
0 < VOUT ≤ 0.3VDD
-12 VDD
mA
0.3VDD < VOUT ≤ 0.9VDD
-17.1(VDD-VOUT)
mA
IOH (AC)
Switching Current High
0.7VDD < VOUT ≤ VDD
Equation C
mA
(Test Point)
VOUT = 0.7VDD
-32 VDD
mA
VDD > VOUT ≥ 0.6VDD
16VDD
mA
0.6VDD > VOUT > 0.1VDD
26.7VOUT
mA
IOL (AC)
Switching Current Low
0.18VDD > VOUT > 0
Equation D
mA
(Test Point)
VOUT=0.18VDD
38VDD
mA
ICL
Low Clamp Current
-3 < VIN ≤ -1
-25+(VIN+1)/0.015
mA
ICH
High Clamp Current
VDD+4 > VIN > VDD+1
25+(VIN-VDD-1)/0.015
mA
slewr
Output Rise Slew Rate
0.2VDD-0.6VDD load
1
4
V/ns
slewf
Output Fall Slew Rate
0.6VDD-0.2VDD load
1
4
V/ns
Notes:
1.
See PCI specification.
2.
PCI specification output load is used.
Table 19: LPC Mode Interface Reset Timing Parameters, VDD=3.0-3.6V
Symbol
Parameter
Min
Max
Units
TPRST
VDD Stable to Reset Low
1
ms
TKRST
Clock Stable to Reset Low
100
µs
TRSTP
RST# Pulse Width
100
ns
TRSTF
RST# Low to Output Float
48
ns
TRST
(1)
RST# High to LFRAME# Low
1
µs
TRSTE
RST# Low to Reset During Erase or Program
10
µs
RST# or INIT# Slew Rate
50
mV/ns
Notes:
1.
There will be a latency of TRSTE if a reset procedure is performed during a Program or Erase operation.
Figure 7: Reset Timing Diagram
T
KRST
T
PRST
T
RST
T
RSTF
T
RSTE
T
RSTP
Program or Erase
Operation Aborted
V
DD
LCLK
RST#/INIT#
LAD[3:0]
LFRAME#


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