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A49LF040 Datasheet(PDF) 14 Page - AMIC Technology

Part No. A49LF040
Description  4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory
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Maker  AMICC [AMIC Technology]
Homepage  http://www.amictechnology.com
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A49LF040 Datasheet(HTML) 14 Page - AMIC Technology

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A49LF040
PRELIMINARY
(August, 2004, Version 0.1)
13
AMIC Technology, Corp.
Figure 3: System Memory Map and Device Memory Map for A49LF040
Block 7
(64K Bytes)
000000
00FFFF
010000
01FFFF
020000
02FFFF
030000
03FFFF
040000
04FFFF
050000
05FFFF
060000
06FFFF
070000
07FFFF
Block 6
(64K Bytes)
Block 5
(64K Bytes)
Block 4
(64K Bytes)
Block 3
(64K Bytes)
Block 2
(64K Bytes)
Block 1
(64K Bytes)
Block 0
(64K Bytes)
TBL#
Device Memory
WP#
for Block 6 ~ 0
A49LF040
Table 11: Software Data Protection Command Definition
Notes:
1.
LPC Mode uses consecutive Write cycles to complete a command sequence; A/A Mux Mode uses consecutive bus cycles to complete a
command sequence.
2.
YYYY = A[31:16]. In LPC mode, during SDP command sequence, YYYY must be within memory address range specified in Table 5. In A/A
Mux mode, YYYY can be VIL or VIH, but no other value.
3.
Chip erase is available in A/A Mux Mode only.
4.
BA: Block Erase Address.
5.
Either 30H or 50H are acceptable for Block Erase.
6.
PA: Program Byte Address; PD: Byte data to be programmed.
7.
Both Product ID Exit commands are equivalent.
1
st Cycle(1)
2
nd Cycle
3
rd Cycle
4
th Cycle
5
th Cycle
6
th Cycle
Command
Bus
Cycles
Addr
(2)
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Block Erase
6
YYYY 5555H
AAH
YYYY 2AAAH
55H
YYYY 5555H
80H
YYYY 5555H
AAH
YYYY 2AAAH
55H
BA
(4)
30H/50H
(5)
Chip Erase
(3)
6
YYYY 5555H
AAH
YYYY 2AAAH
55H
YYYY 5555H
80H
YYYY 5555H
AAH
YYYY 2AAAH
55H
YYYY 5555H
10H
Byte Program
4
YYYY 5555H
AAH
YYYY 2AAAH
55H
YYYY 5555H
A0H
PA
(6)
PD
(6)
Product ID Entry
3
YYYY 5555H
AAH
YYYY 2AAAH
55H
YYYY 5555H
90H
Product ID Exit
(7)
1
XXXX XXXXH
F0H
Product ID Exit
(7)
3
YYYY 5555H
AAH
YYYY 2AAAH
55H
YYYY 5555H
F0H


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