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A49LF040 Datasheet(PDF) 13 Page - AMIC Technology

Part No. A49LF040
Description  4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory
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Maker  AMICC [AMIC Technology]
Homepage  http://www.amictechnology.com
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A49LF040 Datasheet(HTML) 13 Page - AMIC Technology

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A49LF040
PRELIMINARY
(August, 2004, Version 0.1)
12
AMIC Technology, Corp.
to read I/O7 will produce a ‘0’. Once the internal Erase
operation is completed, I/O7 will produce a ‘1’. The Data#
Polling is valid after the rising edge of fourth WE# pulse for
Program operation. For Block- or Chip-Erase, the Data#
Polling is valid after the rising edge of sixth WE# pulse. See
Figure 12 for Data# Polling timing diagram. Proper status will
not be given using Data# Polling if the address is in the
invalid range.
Toggle Bit (I/O6)
During the internal Program or Erase operation, any
consecutive attempts to read I/O6 will produce alternating ‘0’s
and ‘1’s, i.e., toggling between 0 and 1. When the internal
Program or Erase operation is completed, the toggling will
stop. The device is then ready for the next operation. The
Toggle Bit is valid after the rising edge of fourth WE# pulse
for Program operation. For Block- or Chip-Erase, the Toggle
Bit is valid after the rising edge of sixth WE# pulse. See
Figure 13 for Toggle Bit timing diagram.
Data Protection
The A49LF040 device provides both hardware and software
features to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# pulse of less than 5 ns will
not initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, WE# high will inhibit the
Write operation. This prevents inadvertent writes during
power-up or power-down.
Software Data Protection (SDP)
The A49LF040 provides the JEDEC approved Software Data
Protection scheme for all data alteration operation, i.e.,
Program and Erase. Any Program operation requires the
inclusion of a series of three-byte sequences. The three-byte
load sequence is used to initiate the Program operation,
providing
optimal
protection
from
inadvertent
Write
operations, e.g., during the system power-up or power-down.
Any Erase operation requires the inclusion of a six-byte load
sequence. The A49LF040 device is shipped with the
Software Data Protection permanently enabled. See Table
11 for the specific software command codes. During SDP
command sequence, invalid commands will abort the device
to Read mode, within TRC.
Electrical Specifications
The AC and DC specifications for the LPC Interface signals
(LAD[3:0], LCLK, LFRAME#, and RST#) as defined in
Section 4.2.2 of the PCI Local Bus Specification, Rev. 2.1.
Refer to Table 12 for the DC voltage and current
specifications. Refer to the specifications on Table 13 to
Table 22 for Clock, Read/Write, and Reset operations.
Product Identification
The product identification mode identifies the Manufacturer
ID, Continuation ID, and Device ID of the A49LF040. See
Table 9 for detail information.


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