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A43L1616 Datasheet(PDF) 4 Page - AMIC Technology

Part No. A43L1616
Description  1M X 16 Bit X 2 Banks Synchronous DRAM
Download  44 Pages
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Manufacturer  AMICC [AMIC Technology]
Direct Link  http://www.amictechnology.com
Logo AMICC - AMIC Technology

A43L1616 Datasheet(HTML) 4 Page - AMIC Technology

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A43L1616
PRELIMINARY
(August, 2005, Version 0.0)
3
AMIC Technology, Corp.
Pin Descriptions
Symbol
Name
Description
CLK
System Clock
Active on the positive going edge to sample all inputs.
CS
Chip Select
Disables or Enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE
Clock Enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one clock + tss prior to new command.
Disable input buffers for power down in standby.
A0~A10
Address
Row / Column addresses are multiplexed on the same pins.
Row address : RA0~RA10, Column address: CA0~CA8
BA
Bank Select Address
Selects bank to be activated during row address latch time.
Selects band for read/write during column address latch time.
RAS
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column Address
Strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE
Write Enable
Enables write operation and Row precharge.
DQMi
Data Input/Output
Mask
Makes data output Hi-Z, t SHZ after the clock and masks the output.
Blocks data input when DQM active.
DQ0-31
Data Input/Output
Data inputs/outputs are multiplexed on the same pins.
VDD/VSS
Power
Supply/Ground
Power Supply: +3.3V ± 0.3V/Ground
VDDQ/VSSQ
Data Output
Power/Ground
Provide isolated Power/Ground to DQs for improved noise immunity.
NC/RFU
No Connection


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