A43E06321 datasheet(35/46 Pages) AMICC

Part #	A43E06321

Description	512K X 32 Bit X 2 Banks Low Power Synchronous DRAM

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Manufacturer	AMICC [AMIC Technology]

Direct Link	http://www.amictechnology.com

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35 / 46 page

A43E06321

PRELIMINARY

(July, 2005, Version 0.0)

34

AMIC Technology, Corp.

High

0

1

2

3

4567

89

10

11

12

13

14

15

16

17

18

19

CLOCK

CKE

CS

RAS

CAS

ADDR

BA

Row Active

(A-Bank)

: Don't care

A10/AP

WE

QAb1

QAb0

DBc0

DQM

QAb1

QAb0

DBc0

QAd0

DQ

(CL=2)

QAd0

DQ

(CL=3)

Write with

Auto Precharge

(B-Bank)

Write

(A-Bank)

Row Active

(A-Bank)

DAa0

QAd1

DAa0

QAd1

* Note 2

Row Active

(B-Bank)

Read with

Auto Precharge

(A-Bank)

Read

(A-Bank)

Precharge

(A-Bank)

RAa

CAa

RAc

RBb

CAb

CBc

CAd

RAa

RAc

RBb

Burst Read Single Bit Write Cycle @Burst Length=2, BRSW

* Note : 1. BRSW mode is enabled by setting A9 “High” at MRS (Mode Register Set).

At the BRSW Mode, the burst length at write is fixed to “1” regardless of programed burst length.

2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated.

Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command,

The next cycle starts the precharge.

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