MC80F0104/0204
Preliminary
76
Mar. 2005 Ver 0.2
16.3 Communication operation
The transmit operation is enabled when bit 7 (TXE) of the
asynchronous serial interface mode register (ASIMR) is
set to 1. The transmit operation is started when transmit
data is written to the transmit shift register (TXR). The tim-
ing of the transmit completion interrupt request is shown in
Figure 16-6 .
The receive operation is enabled when bit 6 (RXE) of the
asynchronous serial interface mode register (ASIMR) is
set to 1, and input via the RxD pin is sampled. The serial
clock specified by ASIMR is used to sample the RxD pin.
Once reception of one data frame is completed, a receive
completion interrupt request (INT_RX) occurs. Even if an
error has occurred, the receive data in which the error oc-
curred is still transferred to RXR. When ASIMR bit 1 (IS-
RM) is cleared to 0 upon occurrence of an error, and
INT_RX occurs. When ISRM bit is set to 1, INT_RX does
not occur in case of error occurrence. Figure 16-6 shows
the timing of the asynchronous serial interface receive
completion interrupt request.
Figure 16-6 UART data format and interrupt timing diagram
D0
D1
TxD
TX
D2
RxD
D4
D3
D6
D5
D7
Parity
INTERRUPT
Stop
1 data frame
character bits
1 data frame consists of following bits.
- Start bit : 1 bit
- Character bits : 8 bits
- Parity bit : Even parity, Odd parity, Zero parity, No parity
- Stop bit(s) : 1 bit or 2 bits
RX
INTERRUPT
Start
1. Stop bit Length : 1 bit
D0
D1
TxD
TX
D2
RxD
D4
D3
D6
D5
D7
Parity
INTERRUPT
Stop
1 data frame
character bits
RX
INTERRUPT
Start
2. Stop bit Length : 2 bit
D0
D1
TxD
TX
D2
RxD
D4
D3
D6
D5
D7
INTERRUPT
1 data frame
character bits
RX
INTERRUPT
Start
3. Stop bit Length : 1 bit, No parity
Stop
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