MC80F0104/0204
Preliminary
72
Mar. 2005 Ver 0.2
Figure 16-2 Baud Rate Generator Block Diagram
16.2 Serial Interface Configuration
The UART interface consists of the following hardware.
Transmit shift register (TXR)
This is the register for setting transmit data. Data written to
TXR is transmitted as serial data. When the data length is
set as 7 bit, bit 0 to 6 of the data written to TXR are trans-
ferred as transmit data. Writing data to TXR starts the
transmit operation.
TXR can be written by an 8 bit memory manipulation in-
struction. It cannot be read. The RESET input sets TXR to
0FFH.
Receive buffer register (RXR)
This register is used to hold receive data. When one byte of
data is received, one byte of new receive data is transferred
from the receive shift register (RXSR). When the data
length is set as 7 bits, receive data is sent to bits 0 to 6 of
RXR. In this case, the MSB of RXR always becomes 0.
RXR can be read by an 8 bit memory manipulation instruc-
tion. It cannot be written. The RESET input sets RXR to
00H.
Receive shift register
This register converts serial data input via the RXD pin to
paralleled data. When one byte of data is received at this
register cannot be manipulated directly by a program.
Asynchronous serial interface mode register
(ASIMR)
This is an 8 bit register that controls UART serial transfer
operation. ASIMR is set by a 1 bit or 8 bit memory manip-
ulation intruction. The RESET input sets ASIMR to
0000_-00-B. Figure 16-3 shows the format of ASIMR The
RXD / R04 and TXD / R05 pin function selection is shown
in Table 16-2.
Note: Do not switch the operation mode until the current serial
transmit/receive operation has stopped.
MUX
RECEIVE
RxE
Tx_Clock
Rx_Clock
TxE
SEND
5-bit counter
Decoder
5-bit counter
match
match
(BRGCR)
-
TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0
ACLK PIN
fXIN÷2 ~ fXIN÷128
Internal Data Bus
÷2
(Divider)
÷2
(Divider)
Item
Configuration
Register
Transmit shift register (TXR)
Receive buffer register (RXR)
Receive shift register
Control
register
Serial interface mode register (ASIMR)
Serial interface status register (ASISR)
Baud rate generator control register (BRGCR)
Table 16-1 Serial Interface Configuration
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
