MC80F0104/0204
Preliminary
50
Mar. 2005 Ver 0.2
Figure 13-6 Timer Count Example
13.1.2 8-bit Event Counter Mode
In this mode, counting up is started by an external trigger.
This trigger means rising edge of the EC0 or EC1 pin input.
Source clock is used as an internal clock selected with tim-
er mode register TM0 or TM2. The contents of timer data
register TDRn (n = 0,1,2,3) are compared with the contents
of the up-counter Tn. If a match is found, an timer interrupt
request flag TnIF is generated, and the counter is cleared to
“0”. The counter is restart and count up continuously by
every falling edge of the EC0 or EC1 pin input. The maxi-
mum frequency applied to the EC0 or EC1 pin is fXIN/2
[Hz].
In order to use event counter function, the bit 4, 5 of the
Port Selection Register PSR0(address 0F8H) is required to
be set to “1”.
After reset, the value of timer data register TDRn is initial-
ized to "0", The interval period of Timer is calculated as
below equation.
Figure 13-7 Event Counter Mode Timing Chart
Timer 0 (T0IF)
Interrupt
TDR0
TIME
Occur interrupt
Occur interrupt
Occur interrupt
Interrupt period
0
1
2
3
4
5
6
7A
7C
Count Pulse
= 8
µs x (124+1)
7B
MATCH
Example: Make 1ms interrupt using by Timer0 at 4MHz
LDM
TM0,#0FH
; divide by 32
LDM
TDR0,#124
; 8us x (124+1)= 1ms
SET1
T0E
; Enable Timer 0 Interrupt
EI
; Enable Master Interrupt
Period
When
TDR0 = 124D = 7CH
fXIN = 4 MHz
INTERRUPT PERIOD =
4
× 106 Hz
1
× 32 × (124+1) = 1 ms
TM0 = 0000 1111B (8-bit Timer mode, Prescaler divide ratio = 32)
8
µs
(TDR0 = T0)
7C
0
Period (sec)
1
f
XIN
----------- 2 Divide Ratio
(TDRn+1)
×
×
×
=
0
1
2
1
0
n
2
n-1
n
ECn pin input
Up-counter
TDR1
T1IF interrupt
Start count