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M5M5256DP-45LL-W Datasheet(PDF) 2 Page - Mitsubishi Electric Semiconductor

Part No. M5M5256DP-45LL-W
Description  262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
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Maker  MITSUBISHI [Mitsubishi Electric Semiconductor]
Homepage  http://www.mitsubishichips.com
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M5M5256DP-45LL-W Datasheet(HTML) 2 Page - Mitsubishi Electric Semiconductor

   
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MITSUBISHI LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI
ELECTRIC
M5M5256DP,KP,FP,VP,RV -45LL-W,-55LL-W,-70LL-W,
-45XL-W,-55XL-W,-70XL-W
'97.4.7
FUNCTION
FUNCTION TABLE
The operation mode of the M5M5256DP,KP,FP,VP,RV is
determined by a combination of the device control inputs /S,
/W and /OE. Each mode is summarized in the function table.
A write cycle is executed whenever the low level /W
overlaps with the low level /S. The address must be set up
before the write cycle and must be stable during the entire
cycle. The data is latched into a cell on the trailing edge of
/W, /S, whichever occurs first, requiring the set-up and hold
time relative to these edge to be maintained. The output
enable /OE directly controls the output stage. Setting the
/OE at a high level,the output stage is in a high-impedance
state, and the data bus contention problem in the write cycle
is eliminated.
Mode
DQ
Icc
/S
/W
/OE
Non selection
Write
Read
Stand-by
Active
Active
Active
High-impedance
DIN
DOUT
X
X
L
L
L
L
X
L
H
H
H
H
High-impedance
2
A read cycle is executed by setting /W at a high level and
/OE at a low level while /S are in an active state.
When setting /S at a high level, the chip is in a
non-selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a
high-impedance state, allowing OR-tie with other chips and
memory expansion by /S. The power supply current is
reduced as low as the stand-by current which is specified
as Icc3 or Icc4, and the memory data can be held at +2V
power supply, enabling battery back-up operation during
power failure or power-down operation in the non-selected
mode.
VCC
(5V)
GND
(0V)
27
20
22
2
3
4
6
5
7
25
26
1
8
9
10
21
23
24
2
12
11
13
15
16
17
18
19
(512 ROWS X
512 COLUMNS)
32768 WORD
X 8BIT
GENERATOR
CLOCK
A 14
A 13
A 8
A 12
A 6
A 7
A 10
A 0
A 1
A 2
A 3
A 4
A 5
A 11
A 9
/W
/OE
/S
28
14
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
ADDRESS
INPUT
DATA I/O
WRITE CONTROL
INPUT
OUTPUT ENABLE
INPUT
CHIP SELECT
INPUT
BLOCK DIAGRAM


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