CY7C4291V datasheet(9/16 Pages) CYPRESS

Part #	CY7C4291V

Description	16K/32K/64K/128K x 9 Low-Voltage Deep Sync FIFOs

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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9 / 16 page

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

Document #: 38-06013 Rev. *A

Page 9 of 16

Notes:

14. The clocks (RCLK, WCLK) can be free-running during reset.

15. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1.

16. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the

programmable flag offset registers.

Switching Waveforms (continued)

Reset Timing

tRS

tRSR

Q0 − Q8

RS

tRSF

OE=1

OE=0

REN1,

REN2

EF,PAE

FF, PAF

tRSS

tRSR

tRSS

tRSR

tRSS

WEN2/LD

WEN1

[14]

[16]

[15]

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