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STLC1510 Datasheet(PDF) 11 Page - STMicroelectronics |
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STLC1510 Datasheet(HTML) 11 Page - STMicroelectronics |
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11 / 40 page  11/40 STLC1510 5.0 MAIN BLOCK DESCRIPTION The following sections describe the sequence of functions performed by the chip 5.1 Network Interface and Controller (NIF) The Network Interface and Controller block (NIF) is responsible for transferring data between the STLC1510 and the ATM network. The NIF has two interfaces to the backplane: an 8-bit Utopia Level 2 Physical Interface (U2PHY) and a clock and data se- rial interface (CDIF). It communicates with the rest of the STLC1510 via the Lamba Bus. Figure 3. shows a functional/data path block diagram of the NIF (this di- agram does not include all glue logic between the major functional blocks). 37 external pins are re- quired for the U2PHY and CDIF interfaces (19 for the Tx direction, 18 for Rx). Pins are shared between the two interfaces, as they will not both be active at the same time. 5.1.1 Features s Utopia Level 2 8-bit parallel interface. s Up to 9 ATM cells (477 bytes) of rate adaptation buffering for the Utopia Level 2 TX interface. The amount of buffering is programmable via a memory-mapped register. s Up to 2 ATM cells (106 bytes) of rate adaptation buffering for the Utopia Level 2 RX interface. The amount of buffering is programmable via a memory-mapped register. s ATM Transconvergance (TC) layer cell processor with 16-bit data path: performs scrambling/descrambling, HEC calculation, cell delineation with error detection (no error correction) and cell rate decoupling by idle cell insertion/detection. s Clock and Data serial interface. s Implemented as a hardware module on the Lamba bus with an 8-bit data interface and 16- bit control interface. s 4 ATM cells (212 bytes) of rate adaptation buffering in each direction (TX and RX) for interfacing to the Lamba bus. s Pads partial or runt cells (ATM cells of length less than 53 bytes) to 53 bytes in the TX direction to prevent loss of synchronization at the CPE. 5.1.2 External Interface (Pins) The STLC1510 connects to the ATM network via 37 external pins. These are illustrated in Figure 3. Note that the pins TxClk and RxClk are bidirectional and, along with UTxData[0] and URxData[0], are shared between the CDIF and U2PHY 5.1.3 Clock and data serial Interface (CDIF) The STLC1510 can communicate serially to an ATM network through the CDIF. Two serial data lines, one for the Tx path (CO to CPE), the other for the Rx path (CPE to CO), and two respective clocks realize the exchange of information and control signals between the STLC1510 and the network. The CDIF of the STLC1510 has the following at- tributes: s Synchronizes to the ATM network. s Provides Tx and Rx clocks to the ATM network. Transfers data between the ATM network and the STLC1510’s Lamba Bus s Accepts idle ATM cells inserted by the ATM network in the Tx direction. These idle cells are used by the ATM network to adapt to the clock provided to it by the STLC1510. s Generates clock gapping in the Tx direction. This serves two purposes: it is a flow control mechanism to the ATM network chip, and it can be used for the byte alignment. In the byte- alignment role, a clock gap longer than a pre-set threshold indicates that the most significant bit of a byte should be transmitted on the next rising clock edge. This is useful for aligning data bytes to the overhead bits inserted by the STLC1510. In the flow control role, incoming data is not sampled when the clock is off. The threshold used to distinguish between byte alignment and flow control clock gapping is software programmable and has a range of from 0 to 65535 clock cycles (a 16 bit register stores the value). s Generates clock gapping in the Rx direction. This serves as a flow-control mechanism; when there is no data available for transmission to the backplane, the clock is shut off, ensuring that no invalid data bits are sampled by the backplane. |
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Similar Description - STLC1510 |
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