MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

2–1

REV 2

12/93

3Bit 4:1 Multiplexer

The MC10E/100E171 contains three 4:1 multiplexers with differential

outputs. Separate Select controls are provided for the leading 2:1 mux

pairs (see logic symbol). The three Select inputs control which one of the

four data inputs in each case is propagated to the corresponding output.

PIN NAMES

Pin

Function

D0x – D2x

Data Inputs

SEL1A, SEL1B

First-stage Select Inputs

SEL2

Second-stage Select Input

Q0 – Q2

True Output

Q0 – Q2

Inverted Output

FUNCTION TABLE

Pin

State

Operation

SEL2

H

Output c/d data

SEL1A

H

Input d data

SEL1B

H

Input b data

MC10E171

MC100E171

3-BIT 4:1

MULTIPLEXER

FN SUFFIX

PLASTIC PACKAGE

CASE 776-02

D0b

D0c

D0d VCCO

VCCO

D2a

D2b

D2c

D2d

D1a

D1d

D0a

D1b

LOGIC DIAGRAM

SEL1A

SEL1B

SEL2

VEE

NC

NC

D1c

26

27

28

2

3

4

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

5

6

7

8

9

10

Q2

Q2

VCC

Q1

Q1

VCCO

Q0

Q0

D0a

D0b

D0c

D0d

D1a

D1b

D1c

D1d

D2a

D2b

D2c

D2d

SEL1A

SEL1B

SEL2

Q0

Q0

Q1

Q1

Q2

Q2

2:1

MUX

SEL

2:1

MUX

SEL

2:1

MUX

SEL

2:1

MUX

SEL

2:1

MUX

SEL

2:1

MUX

SEL

2:1

MUX

SEL

2:1

MUX

SEL

2:1

MUX

SEL

1

Pinout: 28-Lead PLCC (Top View)

* All VCC and VCCO pins are tied together on the die.