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CAT24WC66 Datasheet(PDF) 4 Page - Catalyst Semiconductor |
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CAT24WC66 Datasheet(HTML) 4 Page - Catalyst Semiconductor |
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CAT24WC66 4 Doc. No. 1037, Rev. H FUNCTIONAL DESCRIPTION The CAT24WC66 supports the I2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT24WC66 operates as a Slave device. Both the Master device and Slave device can operate as either transmitter or receiver, but the Master device controls which mode is activated. PIN DESCRIPTIONS SCL: Serial Clock The serial clock input clocks all data transferred into or out of the device. SDA: Serial Data/Address The bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. A0, A1, A2: Device Address Inputs These pins are hardwired or left unconnected (for hardware compatibility with CAT24WC16). When hardwired, up to eight CAT24WC66 devices may be addressed on a single bus system (refer to Device Addressing ). When the pins are left unconnected, the default values are zeros. WP: Write Protect This input, when tied to GND, allows write operations to the entire memory. When this pin is tied to Vcc, the top 1/4 array of memory is write protected. When left floating, memory is unprotected. Figure 3. Start/Stop Timing Figure 2. Write Cycle Timing Figure 1. Bus Timing START BIT SDA STOP BIT SCL tWR STOP CONDITION START CONDITION ADDRESS ACK 8TH BIT BYTE n SCL SDA tHIGH SCL SDA IN SDA OUT tLOW tF tLOW tR tBUF tSU:STO tSU:DAT tHD:DAT tHD:STA tSU:STA tAA tDH |
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