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CAT24FC65 Datasheet(PDF) 1 Page - Catalyst Semiconductor

Part No. CAT24FC65
Description  64K-Bit I2C Serial CMOS EEPROM with Partial Array Write Protection
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Maker  CATALYST [Catalyst Semiconductor]
Homepage  http://www.catalyst-semiconductor.com
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CAT24FC65 Datasheet(HTML) 1 Page - Catalyst Semiconductor

 
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© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
CAT24FC65, CAT24FC66
64K-Bit I2C Serial CMOS EEPROM with Partial Array Write Protection
Doc. No. 1047, Rev. H
PIN FUNCTIONS
Pin Name
Function
A0, A1, A2
Address Inputs
SDA
Serial Data/Address
SCL
Serial Clock
WP
Write Protect
VCC
+2.5V to +5.5V Power Supply
VSS
Ground
NC
No Connect
DESCRIPTION
The CAT24FC65/66 is a 64k-bit Serial CMOS EEPROM
internally organized as 8,192 words of 8 bits each.
Catalyst’s advanced CMOS technology substantially
reduces device power requirements.
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
The CAT24FC65/66 features a 64-byte page write
buffer. The device operates via the I2C bus serial
interface and is available in 8-pin DIP, SOIC, TSSOP
and TDFN packages.
PIN CONFIGURATION
BLOCK DIAGRAM
I Fast mode I2C bus compatible*
I Max clock frequency:
- 400KHz for VCC=2.5V to 5.5V
I Schmitt trigger filtered inputs for
noise suppression
I Low power CMOS technology
I 64-byte page write buffer
I Self-timed write cycle with auto-clear
I Industrial and automotive temperature ranges
FEATURES
DIP Package (P, L, GL)
I 5 ms max write cycle time
I Write protect feature
– Bottom 1/4 array protected when WP at V
IH
(CAT24FC65)
– Top 1/4 array protected when WP at V
IH
(CAT24FC66)
I 1,000,000 program/erase cycles
I 100 year data retention
I 8-pin DIP, 8-pin SOIC (JEDEC), 8-pin SOIC
(EIAJ), 8-pin TSSOP and TDFN packages
TDFN Package (RD2, ZD2)
1
2
3
4
8
7
6
5
A0
A1
A2
VSS
VCC
WP
SCL
SDA
(Top View)
DOUT
ACK
SENSE AMPS
SHIFT REGISTERS
CONTROL
LOGIC
WORD ADDRESS
BUFFERS
START/STOP
LOGIC
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
EEPROM
128X512
VCC
EXTERNAL LOAD
COLUMN
DECODERS
XDEC
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
VSS
WP
SCL
SDA
128
512
A0
A1
A2
A1
A2
VSS
A1
A2
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
A0
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
VSS
A0
A1
A2
A0
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
VSS
TSSOP Package (U, Y, GY)
SOIC Package
(J, W, K, X, GW, GX)


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