DS80C410-FNY+ datasheet(3/102 Pages) DALLAS

Part #	DS80C410-FNY+

Description	Network Microcontrollers with Ethernet and CAN

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Manufacturer	DALLAS [Dallas Semiconductor]

Direct Link	https://www.maximintegrated.com/en.html

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DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN

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Note 1:

Specifications to -40°C are guaranteed by design and not production tested.

Note 2:

The user should note that this part is tested and guaranteed to operate down to VCC3 = 3.0V and VCC1 = 1.62V, while the reset

thresholds for those supplies, VRST3 and VRST1 respectively, may be above or below those points. When the reset threshold for a

given supply is greater than the guaranteed minimum operating voltage, that reset threshold should be considered the minimum

operating point since execution ceases once the part enters the reset state. When the reset threshold for a given supply is lower

than the guaranteed minimum operating voltage, there exists a range of voltages for either supply, (VRST3 < VCC3 < 1.62V) or (VRST1

< VCC1 < 3.0V), where the processor’s operation is not guaranteed, and the reset trip point has not been reached. This should not

be an issue in most applications, but should be considered when proper operation must be maintained at all times. For these

applications, it may be desirable to use a more accurate external reset.

Note 3:

While the specifications for VPFW3 and VRST3 overlap, the design of the hardware makes it such that this is not possible. Within the

ranges given, there is a guaranteed separation between these two voltages.

Note 4:

Current measured with 75MHz clock source on XTAL1, VCC3 = 3.6V, VCC1 = 2.0V, EA and RST = 0V, Port0 = VCC3, all other pins

disconnected.

Note 5:

While the specifications for VPFW1 and VRST1 overlap, the design of the hardware makes it such that this is not possible. Within the

ranges given, there will be a guaranteed separation between these two voltages.

Note 6:

Certain pins exhibit stronger drive capability when being used to address external memory. These pins and associated memory

interface function (in parentheses) are as follows: Port 3.6-3.7 (

WR, RD), Port 4 (CE0-3, A16-A19), Port 5.4-5.7 (PCE0-3), Port 6.0-

6.5 (

CE4-7, A20, A21), Port 7 (demultiplexed mode A0-A7).

Note 7:

This measurement reflects the weak I/O pullup state that persists following the momentary strong 0 to 1 port pin drive (VOH2). This

I/O pin state can be achieved by applying RST = VCC3.

Note 8:

The measurement reflects the momentary strong port pin drive during a 0-to-1 transition in I/O mode. During this period, a one shot

circuit drives the ports hard for two clock cycles. A weak pullup device (VOH1) remains in effect following the strong two-clock cycle

drive. If a port 4 or 6 pin is functioning in memory mode with pin state of 0 and the SFR bit contains a 1, changing the pin to an I/O

mode (by writing to P4CNT, for example) does not enable the two-cycle strong pullup.

Note 9:

Port 3 pins 3.6 (

WR) and 3.7(RD) have a stronger than normal pullup drive for only one system clock period following the transition

of either

WR or RD from a 0 to a 1.

Note 10:

This is the current required from an external circuit to hold a logic low level on an I/O pin while the corresponding port latch bit is set

to 1. This is only the current required to hold the low level; transitions from 1 to 0 on an I/O pin also have to overcome the transition

current.

Note 11:

Following the 0 to 1 one-shot timeout, ports in I/O mode source transition current when being pulled down externally. It reaches a

maximum at approximately 2V.

Note 12:

During external addressing mode, weak latches are used to maintain the previously driven state on the pin until such time that the

Port 0 pin is driven by an external memory source.

Note 13:

The OW pin (when configured to output a 1) at VIN = 5.5V, EA, MUX, and all MII inputs (TXCLk, RXCLk, RX_DV, RX_ER, RXD[3:0],

CRS, COL, MDIO) at VIN = 3.6V.

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