MT88L70

Data Sheet

3

Zarlink Semiconductor Inc.

Functional Description

The MT88L70 monolithic DTMF receiver offers small size, low power consumption and high performance, with 3

volt operation. Its architecture consists of a bandsplit filter section, which separates the high and low group tones,

followed by a digital counting section which verifies the frequency and duration of the received tones before passing

the corresponding code to the output bus.

Filter Section

Separation of the low-group and high group tones is achieved by applying the DTMF signal to the inputs of two

sixth-order switched capacitor bandpass filters, the bandwidths of which correspond to the low and high group

frequencies. The filter section also incorporates notches at 350 and 440 Hz for exceptional dial tone rejection. Each

filter output is followed by a single order switched capacitor filter section which smooths the signals prior to limiting.

Limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of

unwanted low-level signals. The outputs of the comparators provide full rail logic swings at the frequencies of the

incoming DTMF signals.

Decoder Section

Following the filter section is a decoder employing digital counting techniques to determine the frequencies of the

incoming tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm

protects against tone simulation by extraneous signals such as voice while providing tolerance to small frequency

deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of

immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. When the

detector recognizes the presence of two valid tones (this is referred to as the “signal condition” in some industry

specifications) the “Early Steering” (ESt) output will go to an active state. Any subsequent loss of signal condition

will cause ESt to assume an inactive state (see “Steering Circuit”).

Steering Circuit

Before registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as character

recognition condition). This check is performed by an external RC time constant driven by ESt. A logic high on ESt

latching its corresponding 4-bit code (see Table 1) into the output latch. At this point the GT output is activated and

output latch to settle, the delayed steering output flag (StD) goes high, signalling that a received tone pair has been

registered. The contents of the output latch are made available on the 4-bit output bus by raising the three state

control input (TOE) to a logic high. The steering circuit works in reverse to validate the interdigit pause between

signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal

interruptions (dropout) too short to be considered a valid pause. This facility, together with the capability of selecting

17

19

St/GT

St causes the device to register the detected tone pair and update the output latch. A voltage

external steering time-constant; its state is a function of ESt and the voltage on St.

18

20

Positive power supply (Input). +3 V typical.

7, 16

NC

No Connection.

Pin Description

Pin #

Name

Description

18

20