DS90C385A MTD56 (TSSOP) Package Pin Descriptions — FPD Link

Transmitter

Pin Name

I/O

No.

Description

TxIN

I

28

LVTTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines — FPLINE,

FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).

TxOUT+

O

4

Positive LVDS differentiaI data output.

TxOUT−

O

4

Negative LVDS differential data output.

TxCLKIN

I

1

LVTTL Ievel clock input. Pin name TxCLK IN.

R_FB

I

1

LVTTL Ievel programmable strobe select (See Table 1).

TxCLK OUT+

O

1

Positive LVDS differential clock output.

TxCLK OUT−

O

1

Negative LVDS differential clock output.

PWR DOWN

I

1

LVTTL level input. When asserted (low input) TRI-STATE the outputs, ensuring low current at

power down.

V

CC

I

3

Power supply pins for LVTTL inputs.

GND

I

5

Ground pins for LVTTL inputs.

PLL V

CC

I

1

Power supply pin for PLL.

PLL GND

I

2

Ground pins for PLL.

LVDS V

CC

I

1

Power supply pin for LVDS outputs.

LVDS GND

I

3

Ground pins for LVDS outputs.

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