ComLink™ Series
CY2DL814
Document #: 38-07057 Rev. *A
Page 4 of 8
Table 8. D.C Electrical Characteristics: 3.3V–LVTTL/LVCMOS Input
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
VIH
Input High Voltage
Guaranteed Logic High Level
2
V
VIL
Input Low Voltage
Guaranteed Logic Low Level
0.8
V
IIH
Input High Current
VDD = Max.
VIN = 2.7V
1
µA
IIL
Input Low Current
VDD = Max.
VIN = 0.5V
–1
µA
II
Input High Current
VDD = Max., VIN = VDD(Max.)
20
µA
VIK
Clamp Diode Voltage
VDD = Min., IIN = –18 mA
–0.7
–1.2
V
VH
Input Hysteresis
80
mV
Table 9. D.C Electrical Characteristics: 3.3V–LVDS OUTPUT
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
I VOD I
Differential output voltage p-p
VDD = 3.3V, VIN = VIH, or VIL
RL = 100 ohm
0.25
0.45
V
VOC(SS)
Steady-state common-mode
output voltage
226
mV
Delta
VOC(SS)
Change in VOC(SS) between
logic states
–50
3
50
mV
VOC(PP)
Peak to peak common mode
output voltage
150
mV
IOS
Output short circuit
QA = 0V or QB = 0V
–20
mA
Voh
Output voltage high
RL = 100 ohm
1475
mV
Vol
Output voltage low
925
mV
Table 10. AC Parameters
Parameter
Description
Conditions
Min. Typ. Max. Unit
Rise Time
Pin control (pin 3) logic is “FALSE”
defaulting to 100 ohm output drivers.
Differential 20% to 80%
CL–10 pF
RL and CL to GND
3 CL = Cintrinsic and Cexternal
RL = 100 ohm
1.4
ns
Fall Time
1.4
ns
Rise Time
Pin control (pin 3) logic is “True”
defaulting to 50 ohm output drivers.
Differential 20% to 80%
CL–10 pF
RL and CL to GND
3 CL = Cintrinsic and Cexternal
RL = 50 ohm
Output boost
350
600
ps
Fall Time
350
600
ps
Table 11. AC Switching Characteristics @ 3.3 V (VDD = 3.3V ±5%, Temperature = –40°C to +85°C)
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
IN [+,-] to Q[A,B] Data and Clock Speed
tPLH
Propagation Delay – Low to High
VOD = 100 mV
3
4
5
ns
tPHL
Propagation Delay – High to Low
3
4
5
ns
Tpd
Propagation Delay
3
4
5
ns
IN [1,2] to Q[A,B] Control Speed
TPe
Enable (EN) to functional operation
6
ns
Tpd
Functional operation to Disable
5
ns
Q[A,B] Output Skews
tSK(0)
Output Skew: Skew between outputs of the same
package (in phase)
0.2
ns
tSK(p)
Pulse Skew: Skew between opposite transitions of the
same output (tPHL–tPLH)
0.2
ns
tSK(t)
Package Skew: Skew between outputs of different
packages at the same power supply voltage, temper-
ature and package type. Same input signal level and
output load.
VID = 100 mV
1
ns
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