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CY28341
Document #: 38-07367 Rev. *A
Page 18 of 21
For Differential CPU Output Signals (with P4 Processor SELP4_K7= 1)
The following diagram shows lumped test load configurations
for the differential Host Clock Outputs.
Note:
32. Ideally the probes should be placed on the pins. If there is a transmission line between the test point and the pin for one signal of the pair (e.g., CPU), the same
length transmission line to the other signal of the pair (e.g., AGP) should be added.
Table 10. Signal Loading Table
Clock Name
Max Load (in pF)
REF (0:1), 48MHz (USB), 24_48MHz
20
AGP(0:2), SDRAM (0:11)
30
PCI_F(0:5)
30
DDRT/C (0:5), FBOUT
CPUT/C
See Figure 10
CPUOD_T/C
See Figure 8
CPUCS_T/C
See Figure 9
CLK Measurement Point
R
ref
R
tA1
CPUT
MULTSEL
CLK Measurement Point
R
LA1
R
D
R
LB1
R
LA2
R
LB2
R
tA2
R
tB1
R
tB2
C
LA
C
LB
T
PCB
T
PCB
CPUT#
Figure 10.
Table 11. Lumped Test Load Configuration
Component 0.7V Amplitude Value 1.0V Amplitude Value
RtA1, RtA2
33
Ω
0
Ω
RLA1, RLA2
49.9
Ω∞
TPCB
3” 50
ΩZ3” 50 ΩZ
RLB1, RLB2
∞
63
Ω
RD
∞
470
Ω
RtB1, RtB2
0
Ω
33
Ω
CLA, CLB
2 pF
2 pF
Rref
475
Ω w/mult0 = 1
221
Ω w/mult0 = 0
Group Timing Relationships and Tolerances[32]
Offset (ps) Tolerance (ps) Conditions
tCSAGP CPUCS to
AGP
750
500
CPUCS
Leads
tAP
AGP to
PCI
1,250
500
AGP Leads