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UPD44324092F5-E37-EQ2-A Datasheet(PDF) 11 Page - NEC |
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UPD44324092F5-E37-EQ2-A Datasheet(HTML) 11 Page - NEC |
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11 / 40 page  11 Data Sheet M16780EJ3V0DS µPD44324082, 44324092, 44324182, 44324362 2. Clock starts before VDD/VDDQ stable The clock is supplied from a clock generator. (a) VDD/VDDQ DLL# 30 ns. (MIN.) Clock Stop VDD/VDDQ Stable (< ±0.1 V DC per 50 ns) Fix high (or tied to VDDQ) Unstable Clock (level, frequency) Clock Clock Start Normal Operation Start 1,024 cycles or more Stable Clock (b) VDD/VDDQ DLL# Clock keep running Switched to high after Clock is stable. High or low 30 ns (MIN.) DLL# low VDD/VDDQ Stable (< ±0.1 V DC per 50 ns) Normal Operation Start 1,024 cycles or more Stable Clock Unstable Clock (level, frequency) Clock Clock Start |
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