CY28326
Document #: 38-07616 Rev. *A
Page 7 of 23
Byte 4: Control Register
Bit
@Pup
Name/Pin Affected
Description
7
1
48 MHz
48 MHz Output Enable
0 = Disabled, 1 = Enabled
6
1
24_48 MHz
24_48 MHz Output Enable
0 = Disabled, 1 = Enabled
5
1
PCI5
PCI5 Output Enable
0 = Disabled, 1 = Enabled
4
1
PCI4
PCI4 Output Enable
0 = Disabled, 1 = Enabled
3
1
PCI3
PCI3 Output Enable
0 = Disabled, 1 = Enabled
2
1
PCI2
PCI2 Output Enable
0 = Disabled, 1 = Enabled
1
1
PCI1
PCI1 Output Enable
0 = Disabled, 1 = Enabled
0
1
PCI0
PCI0 Output Enable
0 = Disabled, 1 = Enabled
Byte 5: Control Register
Bit
@Pup
Name/Pin Affected
Description
7
1
AGP2
AGP2 Output Enable
0 = Disabled, 1 = Enabled
6
1
AGP1
AGP1 Output Enable
0 = Disabled, 1 = Enabled
5
1
AGP10
AGP0 Output Enable
0 = Disabled, 1 = Enabled
4
1
25 MHz1
25 MHz1 Output Enable
0 = Disabled, 1 = Enabled
3
1
25 MHz0
25 MHz0 Output Enable
0 = Disabled, 1 = Enabled
2
1
PCIF2
PCIF2 Output Enable
0 = Disabled, 1 = Enabled
1
1
PCIF1
PCIF1 Output Enable
0 = Disabled, 1 = Enabled
0
1
PCIF0
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
Byte 6: Control Register
Bit
@Pup
Name/Pin Affected
Description
7
0
Revision ID Bit 3
Revision ID Bit 3
6
0
Revision ID Bit 2
Revision ID Bit 2
5
0
Revision ID Bit 1
Revision ID Bit 1
4
0
Revision ID Bit 0
Revision ID Bit 0
3
1
Vendor ID Bit 3
Vendor ID Bit 3
2
0
Vendor ID Bit 2
Vendor ID Bit 2
1
0
Vendor ID Bit 1
Vendor ID Bit 1
0
0
Vendor ID Bit 0
Vendor ID Bit 0
Byte 7: Fract Aligner Control Register
Bit
@Pup
Name/Pin Affected
Description
7
1
PCI6
PCI6 Output Enable
0 = Disabled, 1 = Enabled
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