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UPD8871 Datasheet(PDF) 5 Page - NEC

Part No. UPD8871
Description  10680 PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

UPD8871 Datasheet(HTML) 5 Page - NEC

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Data Sheet S15329EJ2V0DS
5
µµµµPD8871
ABSOLUTE MAXIMUM RATINGS (TA =
++++25°°°°C)
Parameter
Symbol
Ratings
Unit
Output drain voltage
VOD
−0.3 to +15
V
Shift register clock voltage
Vφ 1, Vφ 2, Vφ 1L
−0.3 to +8V
Reset gate clock voltage
Vφ RB
−0.3 to +8V
Reset feed-through level clamp
clock voltage
Vφ CLB
−0.3 to +8V
Transfer gate clock voltage
Vφ TG1 to Vφ TG3
−0.3 to +8V
Operating ambient temperature
Note
TA
0 to
+60
°C
Storage temperature
Tstg
−40 to +70
°C
Note
Use at the condition without dew condensation.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (TA =
++++25°°°°C)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Output drain voltage
VOD
11.4
12.0
12.6
V
Shift register clock high level
Vφ 1H, Vφ 2H, Vφ 1LH
4.75
5.0
5.5
V
Shift register clock low level
Vφ 1L, Vφ 2L, Vφ 1LL
−0.3
0
+0.25
V
Reset gate clock high level
Vφ RBH
4.5
5.0
5.5
V
Reset gate clock low level
Vφ RBL
−0.3
0
+0.5
V
Reset feed-through level clamp clock
high level
Vφ CLBH
4.5
5.0
5.5
V
Reset feed-through level clamp clock
low level
Vφ CLBL
−0.3
0
+0.5
V
Transfer gate clock high level
Vφ TG1H to Vφ TG3H
4.75
Vφ 1H
Note
Vφ 1H
Note
V
Transfer gate clock low level
Vφ TG1L to Vφ TG3L
−0.3
0
+0.15
V
Data rate
fφ RB
2.0
10.0
MHz
Note
When Transfer gate clock high level (Vφ TG1H to Vφ TG3H) is higher than Shift register clock high level (Vφ 1H),
Image lag can increase.


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