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UPD29F064115GZ-DB80X-MJH Datasheet(PDF) 22 Page - NEC |
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UPD29F064115GZ-DB80X-MJH Datasheet(HTML) 22 Page - NEC |
22 / 32 page Data Sheet M16062EJ2V0DS 22 µµµµPD29F064115-X Write Cycle (Program / Erase) (1/2) Parameter Symbol -DB80X -DB85X -EB90X Unit Note -EB85X MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. Write cycle time tWC 80 85 90 ns Address setup time (/WE to address) tAS 000 ns Address setup time (/CE to address) tAS 000 ns Address hold time (/WE to address) tAH 45 45 45 ns Address hold time (/CE to address) tAH 45 45 45 ns Input data setup time tDS 45 45 45 ns Input data hold time tDH 000 ns /OE hold time Read tOEH 000 ns Toggle bit, Data polling 10 10 10 Read recovery time before write (/OE to /CE)tGHEL 000 ns Read recovery time before write (/OE to /WE)tGHWL 000 ns /WE setup time (/CE to /WE) tWS 000 ns /CE setup time (/WE to /CE) tCS 000 ns /WE hold time (/CE to /WE) tWH 000 ns /CE hold time (/WE to /CE) tCH 000 ns Write pulse width tWP 35 35 35 ns /CE pulse width tCP 35 35 35 ns Write pulse width high tWPH 30 30 30 ns /CE pulse width high tCPH 30 30 30 ns Word programming operation time tWPG 11 200 11 200 11 200 µs Chip programming operation time tCPG 47 840 47 840 47 840 s Sector erase 4K words sector tSER 0.15 1.0 0.15 1.0 0.15 1.0 s 1,2 operation time 32K words sector 0.5 1.5 0.5 1.5 0.5 1.5 4K words sector 0.5 3.0 0.5 3.0 0.5 3.0 1,3 32K words sector 0.7 5.0 0.7 5.0 0.7 5.0 Chip erase operation time tCER 65.4 205 65.4 205 65.4 205 s 1,2 96.2 678 96.2 678 96.2 678 1,3 Accelerated programming time tACCPG 7 150 7 150 7 150 µs Program / erase cycle 300,000 300,000 300,000 cycle VCC setup time tVCS 200 200 200 µs RY (/BY) recovery time tRB 000 ns /RESET pulse width tRP 500 500 500 ns /RESET high-voltage (VID) hold time from high of tRRB 20 20 20 µs RY (/BY) when sector group is temporarily unprotect /RESET hold time tRH 50 50 50 ns Notes 1. The preprogramming time prior to the erase operation is not included. 2. Program / erase cycle : 100,000 cycles 3. Program / erase cycle : 300,000 cycles |
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