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UPD23C256112A Datasheet(PDF) 8 Page - NEC

Part # UPD23C256112A
Description  NAND INTERFACE 256M-BIT MASK-PROGRAMMABLE ROM
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

UPD23C256112A Datasheet(HTML) 8 Page - NEC

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Data Sheet M15902EJ2V0DS
8
µPD23C256112A
Operation Commands
The following six operation settings are possible by inputting commands from I/O pins.
Command
HEX
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
Command receivable
during Busy
Read mode(1)
00H
L
L
L
L
L
L
L
L
Read mode(2)
01H
L
L
L
L
L
L
L
H
Read mode(3)
Note1
50H
L
H
L
H
LL
LL
Reset
Note2
FFH
HH
HHH
HHH
Status read
70H
L
H
H
H
L
L
L
L
ID read
Note3
90H
H
L
L
H
LL
LL
Notes 1. The data output in read mode (3) is all FFH.
2. The only command that can be executed when the device is Busy is the reset command. Do not set any
of the other commands while the device is Busy.
3. For ID read, input “00H” during the first address cycle after setting a command.
I/O Pin Correspondence Table during Address Input Cycle (Address Setting)
(1) When 00H or 01H command is set [Read mode (1), Read mode (2)]
Command
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1st address cycle
A7
A6
A5
A4
A3
A2
A1
A0
2nd address cycle
A16
A15
A14
A13
A12
A11
A10
A9
3rd address cycle
A24
A23
A22
A21
A20
A19
A18
A17
(2) When 50H command is set [Read mode (3)]
Command
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1st address cycle
×××
×
A3
A2
A1
A0
2nd address cycle
A16
A15
A14
A13
A12
A11
A10
A9
3rd address cycle
A24
A23
A22
A21
A20
A19
A18
A17
Remarks 1. A0 to A24 are internal addresses.
2. Internal address A8 is set internally with command 00H or 01H.
3. When 50H command is set [read mode (3)], the I/O4, I/O5, I/O6, and I/O7 inputs of the 1st address
cycle are VIH or VIL.


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