184pin Unbuffered DDR SDRAM MODULE

M368L1713CTL

Rev. 0.3 May. 2002

GENERAL DESCRIPTION

PIN DESCRIPTION

*

These pins are not used in this module.

Pin Name

Function

A0 ~ A11

Address input (Multiplexed)

BA0 ~ BA1

Bank Select Address

DQ0 ~ DQ63

Data input/output

DQS0 ~ DQS7

Data Strobe input/output

CK0,CK0 ~ CK2,CK2 Clock input

CKE0

Clock enable input

/CS0

Chip select input

RAS

Row address strobe

CAS

Column address strobe

WE

Write enable

DM0 ~ DM7

Data - in mask

VDD

Power supply (2.5V)

VDDQ

Power Supply for DQ S(2.5V)

VSS

Ground

VREF

Power supply for reference

VDDSPD

Serial EEPROM Power

Supply (2.3V to 3.6V)

SDA

Serial data I/O

SCL

Serial clock

SA0 ~ 2

Address in EEPROM

VDDID

VDD identification flag

NC

No connection

PIN CONFIGURATIONS (Front side/back side)

Pin Front

Pin Front

Pin

Front

Pin

Back

Pin

Back

Pin

Back

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

VREF

DQ0

VSS

DQ1

DQS0

DQ2

VDD

DQ3

NC

NC

VSS

DQ8

DQ9

DQS1

VDDQ

CK1

/CK1

VSS

DQ10

DQ11

CKE0

VDDQ

DQ16

DQ17

DQS2

VSS

A9

DQ18

A7

VDDQ

DQ19

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

A5

DQ24

VSS

DQ25

DQS3

A4

VDD

DQ26

DQ27

A2

VSS

A1

*CB0

*CB1

VDD

*DQS8

A0

*CB2

VSS

*CB3

BA1

DQ32

VDDQ

DQ33

DQS4

DQ34

VSS

BA0

DQ35

DQ40

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

VDDQ

/WE

DQ41

/CAS

VSS

DQS5

DQ42

DQ43

VDD

*/CS2

DQ48

DQ49

VSS

/CK2

CK2

VDDQ

DQS6

DQ50

DQ51

VSS

VDDID

DQ56

DQ57

VDD

DQS7

DQ58

DQ59

VSS

NC

SDA

SCL

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

VSS

DQ4

DQ5

VDDQ

DM0

DQ6

DQ7

VSS

NC

NC

NC

VDDQ

DQ12

DQ13

DM1

VDD

DQ14

DQ15

*CKE1

VDDQ

*BA2

DQ20

*A12

VSS

DQ21

A11

DM2

VDD

DQ22

A8

DQ23

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

VSS

A6

DQ28

DQ29

VDDQ

DM3

A3

DQ30

VSS

DQ31

*CB4

*CB5

VDDQ

CK0

/CK0

VSS

*DM8

A10

*CB6

VDDQ

*CB7

VSS

DQ36

DQ37

VDD

DM4

DQ38

DQ39

VSS

DQ44

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

/RAS

DQ45

VDDQ

/CS0

*/CS1

DM5

VSS

DQ46

DQ47

*/CS3

VDDQ

DQ52

DQ53

*A13

VDD

DM6

DQ54

DQ55

VDDQ

NC

DQ60

DQ61

VSS

DM7

DQ62

DQ63

VDDQ

SA0

SA1

SA2

VDDSPD

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

KEY

KEY

M368L1713CTL DDR SDRAM 184pin DIMM

16Mx64 DDR SDRAM 184pin DIMM based on 16Mx8

The Samsung M368L1713CTL is 16M bit x 64 Double Data

Rate SDRAM high density memory modules.

The Samsung M368L1713CTL consists of eight CMOS 16M x

8 bit with 4banks Double Data Rate SDRAMs in 66pin TSOP-

II(400mil) packages mounted on a 184pin glass-epoxy sub-

strate. Four 0.1uF decoupling capacitors are mounted on the

printed circuit board in parallel for each DDR SDRAM. The

M368L1713CTL is Dual In-line Memory Modules and intended

for mounting into 184pin edge connector sockets.

Synchronous design allows precise cycle control with the use

of system clock. Data I/O transactions are possible on both

edges of DQS. Range of operating frequencies, programmable

latencies and burst lengths allow the same device to be useful

for a variety of high bandwidth, high performance memory sys-

tem applications.

•Performance range

•Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V

•Bidirectional data strobe(DQS)

•Differential clock inputs(CK and CK)

•DLL aligns DQ and DQS transition with CK transition

•Programmable Read latency 2, 2.5 (clock)

•Programmable Burst length (2, 4, 8)

•Programmable Burst type (sequential & interleave)

•Edge aligned data output, center aligned data input

•Auto & Self refresh, 15.6us refresh interval(4K/64ms refresh)

•Serial presence detect with EEPROM

•PCB :Height 1250 mil , double sided component

Part No.

Max Freq.

Interface

M368L1713CTL-C(L)B3 166MHz(6ns@CL=2.5)

SSTL_2

M368L1713CTL-C(L)A2 133MHz(7.5ns@CL=2)

M368L1713CTL-C(L)B0 133MHz(7.5ns@CL=2.5)

FEATURE