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COM20019I-LJP Datasheet(PDF) 8 Page - SMSC Corporation

Part # COM20019I-LJP
Description  Low Cost ARCNET(ANSI 878.1) Controller with 2k X 8 On-Board RAM
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Manufacturer  SMSC [SMSC Corporation]
Direct Link  http://www.smsc.com
Logo SMSC - SMSC Corporation

COM20019I-LJP Datasheet(HTML) 8 Page - SMSC Corporation

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Low Cost ARCNET (ANSI 878.1) Controller with 2K x 8 On-Board RAM
Rev. 04-15-05
Page 8
SMSC COM20019I
DATASHEET
Chapter 3 DESCRIPTION OF PIN FUNCTIONS
PLCC PIN
NO.
NAME
SYMBOL
DESCRIPTION
MICROCONTROLLER INTERFACE
1-3
Address
0-2
A0/nMUX,
A1,A2/ALE
Input. On a non-multiplexed mode, A0-A2 are
address input bits. (A0 is the LSB) On a
multiplexed address/data bus, nMUX tied Low,
A1 is left open, and ALE is tied to the Address
Latch Enable signal. A1 is connected to an
internal pull-up resistor.
4-6,8-12
Data 0-7
AD0-AD2, D3-
D7
Input/Output. On a non-multiplexed bus, these
signals are used as the data lines for the
device. On a multiplexed address/data bus,
AD0-AD2 act as the address lines (latched by
ALE) and as the low data lines for the device.
D3-D7 are always used for data only. These
signals are connected to internal pull-up
resistors.
27
nRead/nData
Strobe
nRD/nDS
Input. On a 68XX-like bus, nDS is an active
low signal issued by the microcontroller as the
data strobe signal to strobe the data onto the
bus. On a 80XX-like bus, nRD is an active low
signal issued by the microcontroller to indicate
a read operation.
26
nWrite/
Direction
nWR/DIR
Input. On a 68XX-like bus, DIR is issued by
the microcontroller as the Read/nWrite signal
to determine the direction of data transfer. In
this case, a logic "1" selects a read operation,
while a logic "0" selects a write operation. In
this case, data is actually strobed by the nDS
signal. On an 80XX-like bus, nWR is an active
low signal issued by the microcontroller to
indicate a write operation. In this case, a logic
"0" on this pin, when the COM20019I is
accessed, enables data from the data bus to
be written to the device.
23
nReset in
nRESET
Input. This active low signal executes a
hardware reset.
24
nInterrupt
nINTR
Output. This active low signal is generated by
the COM20019I when an enabled interrupt
condition occurs.
25
nChip Select
nCS
Input. This active low signal selects the
COM20019I for an access.


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