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M470L3324DU0 Datasheet(PDF) 4 Page - Samsung semiconductor

Part No. M470L3324DU0
Description  DDR SDRAM Unbuffered Module 18 4 pin Unbuffered Module based on 512Mb D-die 66 TSOP-II & 54 sTSOP-II with Pb-Free (RoHS compliant)
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Maker  SAMSUNG [Samsung semiconductor]
Homepage  http://www.samsung.com/Products/Semiconductor
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M470L3324DU0 Datasheet(HTML) 4 Page - Samsung semiconductor

 
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DDR SDRAM
256MB, 512MB, 1GB Unbuffered SODIMM
Rev. 0.1 June 2005
Preliminary
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
Speed @CL2
-
133MHz
133MHz
100MHz
Speed @CL2.5
166MHz
166MHz
133MHz
133MHz
Speed @CL3
200MHz
-
-
-
CL-tRCD-tRP
3-3-3
2.5-3-3
2-3-3
2.5-3-3
200Pin Unbuffered SODIMM based on 512Mb D-die (x8, x16)
• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333
• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• PCB : Height - 256MB(non ECC/ECC SS, 1250mil), 512MB/1GB(non ECC DS, 1250mil, ECC DS, 1400mil)
• SSTL_2 Interface
• 66pin TSOP II & 54pin sTSOP II Pb-Free package
RoHS compliant
1.0 Ordering Information
2.0 Operating Frequencies
Part Number
Density
Organization
Component Composition
Height
M470L3324DU0-C(L)CC/B3/A2/B0
256MB
32M x 64
32Mx16 (K4H511638D) * 4EA
1,250mil
M470L6524DU0-C(L)CC/B3/A2/B0
512MB
64M x 64
32Mx16 (K4H511638D) * 8EA
1,250mil
M470L2923DV0-C(L)CC/B3/A2/B0
1GB
128M x 64
64Mx8 (K4H510838D) * 16EA
1,250mil
3.0 Feature


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