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AS4C8M32MD2A-25BPCN Datasheet(PDF) 67 Page - Alliance Semiconductor Corporation

Part # AS4C8M32MD2A-25BPCN
Description  8M x 32 Mobile LPDDR2 Synchronous DRAM (SDRAM)
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Manufacturer  ALSC [Alliance Semiconductor Corporation]
Direct Link  https://www.alliancememory.com
Logo ALSC - Alliance Semiconductor Corporation

AS4C8M32MD2A-25BPCN Datasheet(HTML) 67 Page - Alliance Semiconductor Corporation

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Figure 39. Mode Register Write timing (RL = 3, tMRW = 5)
CK#
T1
T2
Tx
Tx+1
Tx+2
Ty
Ty+1
T0
CK
COMMAND
CA0~9
MR
Addr
MR
Data
MR
Addr
MR
Data
Ty+2
MRW
MRW
ANY
tMRW
tMRW
NOTES:
1. The Mode Register Write Command period is tMRW. No command (other than Nop) is allowed during this period.
2. At time Ty, the device is in the idle state.
CMD not allowed
Figure 40. ZQ Calibration Initialization timing
T1
T2
T3
T4
T5
Tx
Tx+1
T0
MR
Addr
MR
Data
Tx+2
MRW
ANY
tZQINIT
NOTES:
1. The ZQ Calibration Initialization period is tZQINIT. No command (other than Nop) is allowed during this period.
2. CKE must be continuously registered HIGH during the calibration period.
3. All devices connected to the DQ bus should be high impedance during the calibration process.
CMD not allowed
CK#
CK
COMMAND
CA0~9
Figure 41. ZQ Calibration short timing
CK#
T1
T2
T3
T4
T5
Tx
Tx+1
T0
CK
COMMAND
ADDRESS
MR
Addr
MR
Data
Tx+2
MRW
ANY
tZQCS
NOTES:
1. The ZQ Calibration Short period is tZQCS. No command (other than Nop) is allowed during this period.
2. CKE must be continuously registered HIGH during the calibration period.
3. All devices connected to the DQ bus should be high impedance during the calibration process.
CMD not allowed
AS4C8M32MD2A-25BPCN
Confidential
- 67 -
Rev.1.1. May 2019


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