CY25702
Document #: 38-07721 Rev. **
Page 2 of 7
Functional Description
The CY25702 is a Crystal Oscillator (XO).
The device uses a Cypress proprietary PLL to synthesize the
frequency of the embedded input crystal.
The CY25702 uses a programmable configuration memory
array to synthesize output frequency.
The frequency CLK output can be programmed from 10–125
MHz.
The CY25702 is available in a 4-pin plastic SMD packages
with operating temperature range of –20 to 70°C.
Programming Description
Field/Factory-Programmable CY25702
Field/Factory programming is available for samples and
manufacturing by Cypress and its distributors. All requests
must be submitted to the local Cypress Field Application
Engineer (FAE) or sales representative. Once the request has
been processed, you will receive a new part number, samples,
and data sheet with the programmed values. This part number
will be used for additional sample requests and production
orders.
Additional information on the CY25702 can be obtained from
the Cypress web site at www.cypress.com.
Output Frequency, CLK Output (CLK, pin 3)
The frequency at the CLK output is produced by synthesizing
the embedded crystal oscillator frequency input. The range of
synthesized clock is from 1–125MHz when VDD= 5V and
1–90MHz when VDD = 3.3V.
Output Enable or Power Down (OE/PD#, pin 1)
Pin 1 can be programmed as either output enable (OE) or
Power Down (PD#).
Absolute Maximum Rating
Supply Voltage (VDD).....................................–0.5V to +7.0V
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Storage Temperature (Non-condensing) .... –55°C to +100°C
Junction Temperature ................................ –40°C to +125°C
Data Retention @ Tj = 125
°C................................> 10 years
Package Power Dissipation...................................... 350 mW
Pin Definition
Pin
Name
Description
1OE/PD#
Output Enable pin: Active HIGH. If OE = 1, CLK is enabled.
Power Down pin: Active LOW. If PD# = 0, Power Down is enabled.
2
VSS
Power supply ground.
3CLK
Clock output.
4VDD
3.3V or 5.0V power supply.
Table 1. Programming Data Requirement
Pin Function
Output Frequency
Output Enable/Power Down
Power Supply
Pin Name
CLK
OE/PD#
VDD
Pin#
3
1
4
Units
MHz
N/A
V
Program Value
ENTER DATA
ENTER DATA
ENTER DATA
Operating Conditions
Parameter
Description
Min.
Typ.
Max.
Unit
VDD1
Supply Voltage Range
3.00
3.30
3.60
V
VDD2
Supply Voltage Range
4.50
5.00
5.50
V
TA
Ambient Temperature
–20
–
70
°C
CLOAD
Max. Load Capacitance @ pin 3
–
–
15
pF
FCLK1
CLK output frequency, CLOAD = 15 pF, VDD = 5.0V
1.0
–
125
MHz
FCLK2
CLK output frequency, CLOAD = 15 pF, , VDD = 3.3V
1.0
–
90
MHz
TPU
Power-up time for VDD to reach minimum specified
voltage (power ramp must be monotonic)
0.05
–
500
ms
DC Electrical Characteristics
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
VOH1
High Output Voltage
VDD = 5.0V, IOH = –16mA
VDD-0.4
–
–
V
VOL1
Low Output Voltage
VDD= 5.0V , IOL= 16mA
–
–
0.4
V
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
