DP83821VUW datasheet(3/86 Pages) NSC

Part #	DP83821VUW

Description	10/100/1000 Mb/s PCI Ethernet Network Interface Controller

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Manufacturer	NSC [National Semiconductor (TI)]

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2.0 Pin Descriptions

PCI Interface

Symbol

Pin No(s)

Direction

Description

AD31-0

188, 189, 190,

191, 192, 193,

194, 195, 199,

200, 202, 203,

204, 207, 208,

1, 14, 15, 17,

18, 19, 21, 22,

23, 25, 26, 28,

29, 31, 32, 33,

34

I/O

Address and Data: Multiplexed address and data bus. As a bus master, the

DP83821 will drive address during the first bus phase. During subsequent

phases, the DP83821 will either read or write data expecting the target to

increment its address pointer. As a bus target, the DP83821 will decode each

address on the bus and respond if it is the target being addressed.

CBEN3-0

197, 2, 13, 24

I/O

Bus Command/Byte Enable: During the address phase these signals define

the “bus command” or the type of bus transaction that will take place. During

the data phase these pins indicate which byte lanes contain valid data. CBEN0

applies to byte 0 (bits 7-0) and CBEN3 applies to byte 3(bits 31-24).

PCICLK

176

I

Clock: This PCI Bus clock provides timing for all bus phases. The rising edge

defines the start of each phase. The clock frequency ranges from 0 to 33 MHz.

DEVSELN

8

I/O

Device Select: As a target, the DP83821 asserts this signal low when it

recognizes its address after FRAMEN is asserted. As a bus master, the

DP83821 samples this signal to insure that the destination address for the data

transfer is recognized by a PCI target.

FRAMEN

4

I/O

Frame: As a bus master, this signal is asserted low to indicate the beginning

and duration of a bus transaction. Data transfer takes place when this signal is

asserted. It is de-asserted before the transaction is in its final phase. As a

target, the device monitors this signal before decoding the address to check if

the current transaction is addressed to it.

GNTN

185

I

Grant: This signal is asserted low to indicate to the DP83821 that it has been

granted ownership of the bus by the central arbiter. This input is used when the

DP83821 is acting as a bus master.

IDSEL

198

I

Initialization Device Select: This pin is sampled by the DP83821 to identify

when configuration read and write accesses are intended for it.

INTAN

183

O

Interrupt A: This signal is asserted low when an interrupt condition as defined

in the Interrupt Status Register, Interrupt Mask, and Interrupt Enable registers

occurs.

IRDYN

5

I/O

Initiator Ready: As a bus master, this signal will be asserted low when the

DP83821 is ready to complete the current data phase transaction. This signal is

used in conjunction with the TRYDN signal. Data transaction takes place at the

rising edge of PCICLK when both IRDYN and TRDYN are asserted low. As a

target, this signal indicates that the master has put the data on the bus.

PAR

12

I/O

Parity: This signal indicates even parity across AD31-0 and CBEN3-0 including

the PAR pin. As a master, PAR is asserted during address and write data

phases. As a target, PAR is asserted during read data phases.

PERRN

10

I/O

Parity Error: The DP83821 as a master or target will assert this signal low to

indicate a parity error on any incoming data (except for special cycles). As a

bus master, it will monitor this signal on all write operations (except for special

cycles).

REQN

186

O

Request: The DP83821 will assert this signal low to request the ownership of

the bus to the central arbiter.

RSTN

184

I

Reset: When this signal is asserted all outputs of DP83821 will be tri-stated

and the device will be put into a known state.

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