CY22050
Document #: 38-07006 Rev. *D
Page 4 of 9
Reference Crystal Input
The input crystal oscillator of the CY22050 is an important
feature because of the flexibility it allows the user in selecting
a crystal as a reference clock source. The oscillator inverter
has programmable gain, allowing for maximum compatibility
with a reference crystal, based on manufacturer, process,
performance, and quality.
The value of the input load capacitors is determined by eight
bits in a programmable register. Total load capacitance is
determined by the formula:
CapLoad = (CL – CBRD – CCHIP)/0.09375 pF
In CyClocksRT, enter the crystal capacitance (CL). The value
of CapLoad will be determined automatically and programmed
into the CY22050.
If you require greater control over the CapLoad value, consider
using the CY22150F for serial configuration and control of the
input load capacitors. For an external clock source, the default
is 0.
Input load capacitors are placed on the CY22050 die to reduce
external component cost. These capacitors are true
parallel-plate capacitors, designed to reduce the frequency
shift that occurs when non-linear load capacitance is affected
by load, bias, supply, and temperature changes.
Absolute Maximum Conditions
Parameter
Description
Min.
Max.
Unit
VDD
Supply Voltage
–0.5
7.0
V
VDDL
I/O Supply Voltage
–0.5
7.0
V
TS
Storage Temperature[3]
–65
125
°C
TJ
Junction Temperature
125
°C
Package Power Dissipation—Commercial Temp
450
mW
Package Power Dissipation—Industrial Temp
380
mW
Digital Inputs
AVSS – 0.3
AVDD + 0.3
V
Digital Outputs referred to VDD
VSS – 0.3
VDD + 0.3
V
Digital Outputs referred to VDDL
VSS – 0.3
VDDL +0.3
V
ESD
Static Discharge Voltage per MIL-STD-833, Method 3015
2000
V
Recommended Operating Conditions
Parameter
Description
Min.
Typ.
Max.
Unit
VDD
Operating Voltage
3.135
3.3
3.465
V
VDDLHI
Operating Voltage
3.135
3.3
3.465
V
VDDLLO
Operating Voltage
2.375
2.5
2.625
V
TAC
Ambient Commercial Temp
0
70
°C
TAI
Ambient Industrial Temp
–40
85
°C
CLOAD
Max. Load Capacitance VDD/VDDL = 3.3V
15
pF
CLOAD
Max. Load Capacitance VDDL = 2.5V
15
pF
fREFD
Driven REF
1
133
MHz
fREFC
Crystal REF
8
30
MHz
tPU
Power-up time for all VDDs to reach minimum
specified voltage (power ramps must be
monotonic)
0.05
500
ms
Note:
3. Rated for 10 years.
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