1
Note:
1. For LCC/PLCC only: Pins 1 and 17 are common and tied to the die at
tach pad. They should not be used.
Cypress Semiconductor Corporation
D
3901 North First Street
D San Jose D
CA 95134
D 408-943-2600
November 1994
PRELIMINARY
CY27H512
64K x 8 HighSpeed CMOS
EPROM
Logic Block Diagram
Pin Configurations
Features
D
CMOS for optimum speed/power
D
High speed
tAA = 25 ns max. (commercial)
tAA = 35 ns max. (military)
D
Low power
275 mW max.
Less than 85 mW when deselected
D
Bytewide memory organization
D
100% reprogrammable in the
windowed package
D
EPROM technology
D
Capable of withstanding >2001V
static discharge
D
Available in
32pin PLCC
28pin TSOP I
28pin, 600mil plastic or
hermetic DIP
32pin hermetic LCC
Functional Description
The CY27H512 is a highperformance,
512K CMOS EPROM organized in 64
Kbytes. It is available in industrystandard
28pin, 600mil DIP, 32pin LCC and
PLCC, and 28pin TSOP I packages.
These devices offer highdensity storage
combined with40MHzperformance. The
CY27H512 is available in windowed and
opaque packages. Windowed packages al
low the device to be erased with UV light
for 100% reprogrammability.
The CY27H512 is equipped with a power
down chip enable (CE) input and output
enable (OE). When CE is deasserted, the
device powers down to a lowpower stand
by mode. The OE pin threestates the out
puts without putting the device into stand
by mode. While CE offers lower power,
OE providesamorerapidtransitiontoand
from threestated outputs.
The memory cells utilize proven EPROM
floatinggate technology and bytewide in
telligent programming algorithms. The
EPROM cell requires only 12.75 V for the
supervoltage and low programming cur
rentallowsforgangprogramming. Thede
vice allows for each memory location to be
tested 100%, because each location is writ
ten to, erased, and repeatedly exercised
prior to encapsulation. Each device is also
tested for AC performance to guarantee
that the product will meet DC and AC
specification limits after customer pro
gramming.
The CY27H512 is read by asserting both
the CE and the OE inputs. The contents of
the memory location selected by the ad
dress on inputs A15-A0 will appear at the
outputs O7-O0.
Top View
DIP
H5121
H5122
Top View
H5123
PROGRAMMABLE
ARRAY
O0
O1
O7
O2
O4
O3
O5
O6
ADDRESS
DECODER
A0
A1
A2
A3
A4
A5
A6
A8
A7
MULTIPLEXER
A9
A10
A11
A12
A13
A14
A15
OUTPUT ENABLE
DECODER
CE
OE
POWER DOWN
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
24
23
22
21
13
14
25
28
27
26
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
VCC
A14
A13
A8
A9
A11
OE/VPP
A10
CE
O7
O6
O4
O5
O3
15
12
O0
31
4
5
6
7
8
9
10
32 1
30
13
14 15 16 17
26
25
24
23
22
21
11
A6
A5
A4
A3
A2
A1
A0
CE
A9
A11
NC
A10
O7
O6
A8
OE/VPP
1819 20
27
28
29
32
NC
LCC/PLCC[1]