PC133 Clock Generator for SiS630/Pentium
®III & SiS540/Socket7 Applications
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07035 Rev. **
05/02/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
Page 7 of 18
http://www.cypress.com
APPROVED PRODUCT
C9630
Serial Control Registers (Cont.)
Byte 1: CPU Clock Register (1 = enable, 0 = Stopped)
Bit
@Pup
Pin#
Description
7
1
-
Selects Frequency at pin 25
1 = selects 24MHz (default)
0 = selects 48MHz
6
1
-
SSTS, See Table 4, p 11
5
1
-
Reserved for IMI test^
4
1
-
Reserved for IMI test^
3
1
43
CPU2 enable/Stopped
2
1
45
CPU1 enable/Stopped
1
1
46
CPU0 enable/Stopped
0
1
-
Reserved for IMI test^
Byte 2: PCI Clock Register (1 = enable, 0 = Stopped)
Bit
@Pup
Pin#
Description
71
-
Reserved
6
1
14
PCI6 enable/Stopped
5
1
13
PCI5 enable/Stopped
4
1
12
PCI4 enable/Stopped
3
1
11
PCI3 enable/Stopped
2
1
9
PCI2 enable/Stopped
1
1
8
PCI1 enable/Stopped
0
1
7
PCI0 enable/Stopped
Byte 3: SDRAM Clock Register (1 = enable, 0 = Stopped)
Bit
@Pup
Pin#
Description
7
1
32
SDRAM7 enable/Stopped
6
1
31
SDRAM6 enable/Stopped
5
1
29
SDRAM5 enable/Stopped
4
1
28
SDRAM4 enable/Stopped
3
1
21
SDRAM3 enable/Stopped
2
1
20
SDRAM2 enable/Stopped
1
1
18
SDRAM1 enable/Stopped
0
1
17
SDRAM0 enable/Stopped
Byte 4: Additional SDRAM Clock Register (1=enable, 0=Stopped)
Bit
@Pup
Pin#
Description
7
1
25
24_48MHz enable/Stopped
6
1
26
48 MHz enable/Stopped
5
1
41
SDRAM13 enable/Stopped
4
1
40
SDRAM12 enable/Stopped
3
1
38
SDRAM11 enable/Stopped
2
1
37
SDRAM10 enable/Stopped
1
1
35
SDRAM9 enable/Stopped
0
1
34
SDRAM8 enable/Stopped
Byte 5: Peripheral Control (1 = enable, 0 = Stopped)
Bit
@Pup
Pin#
Description
71
-
MBS1, See table 4, p. 11 for
Spread Spectrum
61
-
MBS0, See table 4, p.11 for
Spread Spectrum
5
1
-
S3# *
4
1
-
S2# *
3
1
-
S1# *
2
1
-
S0# *
1
1
48
REF1 enable/Stopped
0
1
2
REF0 enable/Stopped
*Inverted read back of hardware settings.
Byte 6: Reserved Register (1 = enable, 0 = Stopped)
Bit
@Pup
Pin#
Description
7
0
-
Reserved for IMI test^
60
-
50
-
4
0
-
Reserved for IMI test^
3
0
-
Reserved for IMI test
2
1
-
Reserved for IMI test
10
-
N9, MSB
00
-
N8
Byte 7: Dial-a-Frequency® N Register (1 = enable, 0 = Stopped)
Bit
@Pup
Pin#
Description
70
-
N7
60
-
N6
50
-
N5
40
-
N4
30
-
N3
20
-
N2
10
-
N1
0
0
-
N0, LSB
Byte 8: Dial-a-Frequency® R Register (1 = enable, 0 = Stopped)
Bit
@Pup
Pin#
Description
70
-
R6, MSB
60
-
R5
50
-
R4
40
-
R3
30
-
R2
20
-
R1
1
0
-
R0, LSB
0
0
-
1 = Enable SMBus N and R
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