P89LV51RD2FA datasheet(8/77 Pages) PHILIPS

Part #	P89LV51RD2FA

Description	8-bit 80C51 3 V low power 16/32/64 kB Flash microcontroller with 1 kB RAM

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Manufacturer	PHILIPS [NXP Semiconductors]

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Philips Semiconductors

P89LV51RB2/RC2/RD2

8-bit microcontrollers with 80C51 core

Product data

Rev. 04 — 02 December 2004

8 of 77

9397 750 14342

P2.0 to

P2.7

21-28

18-25

24-31

I/O

with internal

pull-up

Port 2: Port 2 is an 8-bit bi-directional I/O port with

internal pull-ups. Port 2 pins are pulled HIGH by the

internal pull-ups when ‘1’s are written to them and can

be used as inputs in this state. As inputs, Port 2 pins that

are externally pulled LOW will source current (IIL)

because of the internal pull-ups. Port 2 sends the

high-order address byte during fetches from external

program memory and during accesses to external Data

Memory that use 16-bit address (MOVX@DPTR). In this

application, it uses strong internal pull-ups when

transitioning to ‘1’s. Port 2 also receives some control

signals and a partial of high-order address bits during

the external host mode programming and veriﬁcation.

P3.0 to

P3.7

10-17

5, 7-13

11, 13-19

I/O

with internal

pull-up

Port 3: Port 3 is an 8-bit bidirectional I/O port with

internal pull-ups. Port 3 pins are pulled HIGH by the

internal pull-ups when ‘1’s are written to them and can

be used as inputs in this state. As inputs, Port 3 pins that

are externally pulled LOW will source current (IIL)

because of the internal pull-ups. Port 3 also receives

some control signals and a partial of high-order address

bits during the external host mode programming and

veriﬁcation.

P3.0

10

5

11

I

RXD: serial input port

P3.1

11

7

13

O

TXD: serial output port

P3.2

12

8

14

I

INT0: external interrupt 0 input

P3.3

13

9

15

I

INT1: external interrupt 1 input

P3.4

14

10

16

I

T0: external count input to Timer/Counter 0

P3.5

15

11

17

I

T1: external count input to Timer/Counter 1

P3.6

16

12

18

O

WR: external data memory write strobe

P3.7

17

13

19

O

RD: external data memory read strobe

PSEN

29

26

32

I/O

Program Store Enable: PSEN is the read strobe for

external program memory. When the device is executing

from internal program memory, PSEN is inactive

(HIGH). When the device is executing code from

external program memory, PSEN is activated twice each

machine cycle, except that two PSEN activations are

skipped during each access to external data memory. A

forced HIGH-to-LOW input transition on the PSEN pin

while the RST input is continually held HIGH for more

than 10 machine cycles will cause the device to enter

external host mode programming.

RST

9

4

10

I

Reset: While the oscillator is running, a HIGH logic state

on this pin for two machine cycles will reset the device. If

the PSEN pin is driven by a HIGH-to-LOW input

transition while the RST input pin is held HIGH, the

device will enter the external host mode, otherwise the

device will enter the normal operation mode.

Table 3:

P89LV51RB2/RC2/RD2 pin description…continued

Symbol

Type

Description

DIP40

TQFP44

PLCC44

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