Integrated Circuit Solution Inc.

7

LPSR018-0D 07/06/2001

IS62LV1024L/LL

Power)

-45

-55

-70

Symbol Parameter

Min. Max.

Min. Max.

Min. Max.

Unit

Write Cycle Time

45

—

55

—

70

—

ns

CE1 to Write End

35

—

50

—

60

—

ns

CE2 to Write End

35

—

50

—

60

—

ns

Address Setup Time to Write End

35

—

50

—

60

—

ns

Address Hold from Write End

0

—

0

—

0

—

ns

Address Setup Time

0

—

0

—

0

—

ns

35

—

40

—

55

—

ns

Data Setup to Write End

25

—

25

—

30

—

ns

Data Hold from Write End

0

—

0

—

0

—

ns

—

15

—

20

0

25

ns

5

—

5

—

5

—

ns

Notes:

1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to 2.2V

and output loading specified in .igure 1.

2. Tested with the load in .igure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to

initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the

rising or falling edge of the signal that terminates the Write.

4. Tested with OE HIGH.

DATA-IN VALID

DATA UNDEFINED

HIGH-Z

ADDRESS

CE1

CE2

WE

DOUT

DIN

AC WAVE.ORMS

WRITE CYCLE NO. 1 (9-

9-

9-

9-