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IDT5V991A Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT5V991A Datasheet(HTML) 7 Page - Integrated Device Technology |
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7 / 8 page  7 COMMERCIALANDINDUSTRIALTEMPERATURERANGES IDT5V991A 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK RE F FB Q O THE R Q IN VE R TED Q RE F D IV ID E D B Y 2 RE F D IV ID E D B Y 4 tJR tREF tPD tSKE W 2 tSK EW 3, 4 tSK EW 1, 3, 4 tSK EW 2, 4 tSK EW 3, 4 tSK EW 3, 4 tSKEW 2 tSKE W PR tSK EW 0, 1 tODC V tODC V tRP W H tRPW L tSKE W PR tSK EW 0, 1 AC TIMING DIAGRAM NOTES: VCCQ/PE: The AC Timing Diagram applies to VCCQ/PE=VCC. For VCCQ/PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the negative edge of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align. Skew: The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 20pF and terminated with 75 Ω to VCC/2. tSKEWPR: The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU. tSKEW0: The skew between outputs when they are selected for 0tU . tDEV: The output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.) tODCV: The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications. tPWH is measured at 2V. tPWL is measured at 0.8V. tORISE and tOFALL are measured between 0.8V and 2V. tLOCK: The time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits. |
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