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TDA3LX Datasheet(PDF) 88 Page - Texas Instruments |
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TDA3LX Datasheet(HTML) 88 Page - Texas Instruments |
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88 / 271 page  88 TDA3MV, TDA3MA, TDA3MD TDA3LX, TDA3LA SPRS964G – JUNE 2016 – REVISED MARCH 2019 www.ti.com Submit Documentation Feedback Product Folder Links: TDA3MV TDA3MA TDA3MD TDA3LX TDA3LA Specifications Copyright © 2016–2019, Texas Instruments Incorporated Table 5-5. Maximum Supported Frequency (continued) Module Clock Sources Instance Name Input Clock Name Clock Type Max. Clock Allowed (MHz) PRCM Clock Name PLL / OSC / Source Clock Name PLL / OSC / Source Name OCP_WP_NOC PICLKOCPL3 Int 266 L3INSTR_L3_GICL K CORE_X2_CLK DPLL_CORE PWMSS1 PWMSS1_GICLK Int & Func 133 L4PER2_L3_GICL K CORE_X2_CLK DPLL_CORE QSPI QSPI_ICLK Int 266 L4PER2_L3_GICL K CORE_X2_CLK DPLL_CORE QSPI_FCLK Func 128 QSPI_GFCLK FUNC_128M_CLK DPLL_PER PER_QSPI_CLK DPLL_PER RTI1 OCP_CLK_PI Int 133 WKUPAON_GICL K CORE_X2_CLK DPLL_CORE RTI_CLK_PI Func 13 RTI1_CLK SYS_CLK1/4 OSC0 SYS_CLK2/4 OSC1 FUNC_32K_CLK OSC0 RTI2 OCP_CLK_PI Int 133 WKUPAON_GICL K CORE_X2_CLK DPLL_CORE RTI_CLK_PI Func 13 RTI2_CLK SYS_CLK1/4 OSC0 SYS_CLK2/4 OSC1 FUNC_32K_CLK OSC0 RTI3 OCP_CLK_PI Int 133 WKUPAON_GICL K CORE_X2_CLK DPLL_CORE RTI_CLK_PI Func 13 RTI3_CLK SYS_CLK1/4 OSC0 SYS_CLK2/4 OSC1 FUNC_32K_CLK OSC0 RTI4 OCP_CLK_PI Int 133 WKUPAON_GICL K CORE_X2_CLK DPLL_CORE RTI_CLK_PI Func 13 RTI4_CLK SYS_CLK1/4 OSC0 SYS_CLK2/4 OSC1 FUNC_32K_CLK OSC0 RTI5 OCP_CLK_PI Int 133 WKUPAON_GICL K CORE_X2_CLK DPLL_CORE RTI_CLK_PI Func 13 RTI5_CLK SYS_CLK1/4 OSC0 SYS_CLK2/4 OSC1 FUNC_32K_CLK OSC0 SD_DAC CLKDAC Func 50 VID_PIX_CLK VID_PIX_CLK DPLL_EVE_VID_D SP SL2 piclk Int IVA_GCLK IVA_GCLK IVA_GFCLK DPLL_IVA SPINLOCK SPINLOCK_ICLK Int 133 L4CFG_L3_GICLK CORE_X2_CLK DPLL_CORE TESOC L3_CLK Func 266 L3MAIN1_L3_GIC LK CORE_X2_CLK DPLL_CORE EXT_CLK Func 50 EXT_CLK TESOC_EXT_CLK DPLL_CORE TIMER1 TIMER1_ICLK Int 133 WKUPAON_GICL K SYS_CLK1 OSC0 ABE_LP_CLK DPLL_DDR TIMER1_FCLK Func 38.4 TIMER1_GFCLK SYS_CLK1 OSC0 FUNC_32K_CLK OSC0 SYS_CLK2 OSC1 XREF_CLK0 xref_clk0 XREF_CLK1 xref_clk1 ABE_GICLK DPLL_DDR |
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