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FS6282-03 Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers

Part # FS6282-03
Description  DUAL PLL CLOCK GENERATOR IC
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Manufacturer  ETC1 [List of Unclassifed Manufacturers]
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AMERICAN MICROSYSTEMS, INC.
October 1999
3
10.1.99
FS6282
FS6282
FS6282
FS6282
Dual PLL Clock Generator IC
Dual PLL Clock Generator IC
Dual PLL Clock Generator IC
Dual PLL Clock Generator IC
ISO9001
ISO9001
ISO9001
ISO9001
Table 5: DC Electrical Specifications
Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are
± 3σfrom typical. Negative currents indicate current flows out of the device.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
Overall
Supply Current, Dynamic, with Loaded
Outputs
IDD
fXTAL = 13.5MHz; CL = 10pF, VDD = 3.6V
30
mA
Crystal Oscillator
Crystal Loading Capacitance
CL(xtal)
As seen by a crystal connected to XIN and
XOUT
18
pF
Clock Outputs (CLKA, CLKB)
zOH
VO = 0.1VDD; output driving high
45
Output Impedance *
zOL
VO = 0.1VDD; output driving low
45
Short Circuit Source Current *
IOSH
VO = 0V; shorted for 30s, max.
-35
mA
Short Circuit Sink Current *
IOSL
VO = 3.3V; shorted for 30s, max.
35
mA
Table 6: AC Timing Specifications
Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are
± 3σfrom typical.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
Overall
Synthesis Error
(unless otherwise noted in Frequency Table)
0
ppm
Clock Outputs (CLKA, CLKB, CLKC)
Duty Cycle *
Ratio of high pulse width (as measured from rising edge to next falling
edge at VDD/2) to one clock period
45
55
%
Jitter, Period (peak-peak) *
tj(∆P)
From rising edge to next rising edge at VDD/2, CL =
10pF
300
ps
Rise Time *
tr
VDD = 3.3V; VO = 0.3V to 3.0V; CL = 10pF
3
ns
Fall Time *
tf
VDD = 3.3V; VO = 3.0V to 0.3V; CL = 10pF
2.5
ns


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