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ADF7901BRU Datasheet(PDF) 4 Page - Analog Devices |
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ADF7901BRU Datasheet(HTML) 4 Page - Analog Devices |
4 / 12 page ADF7901 Preliminary Technical Data Rev. PrD | Page 4 of 12 Parameter1 Min Typ Max Unit PHASE-LOCKED LOOP VCO Gain 30 MHz/V at 384 MHz Spurious7, 3 100 kHz loop BW Integer Boundary –45 −23 dBc Reference −70 −23 dBc Harmonics 3 Second Harmonic VDD = 3.0 V −24 −21 dBc Third Harmonic VDD = 3.0 V −14 −11 dBc All Other Harmonics −18 dBc REFERENCE INPUT Crystal Reference 9.8304 MHz POWER AMPLIFIER PA Output Impedance 97 Ω + 6.4 pF At 384 MHz TIMING INFORMATION Crystal Oscillator to PLL Lock 3 2 3 ms PA Enable to PA ready–PLL Settle8 100 250 µs TEMPERATURE RANGE – TA 0 50 °C 1 Operating temperature range is as follows: 0°C to +50°C. 2 Frequency Deviation = 34 × (9.8304 MHz )/214. Error in the crystal will be reflected in variation in the desired deviation. 3 Not production tested. Based on characterization. 4 The output power can be varied in both ASK/FSK mode by altering the relevant external resistor. 5 Measured using Spectrum Analyzer, 1 MHz span, 100 kHz RBW, MAX HOLD enabled. 6 Maximum power-down current spec applies for the OSC2 pin grounded. 7 Measured > 461.9 kHz away from channel. 8 This spec refers to the time taken for the PLL to regain lock after the PA has been enabled. The PA is should only be enabled after the PLL has settled to the correct frequency. |
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