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MC100EPT24DR2 Datasheet(PDF) 1 Page - ON Semiconductor |
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MC100EPT24DR2 Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 4 page © Semiconductor Components Industries, LLC, 1999 December, 1999 – Rev. 1 1 Publication Order Number: MC100EPT24/D MC100EPT24 LVTTL/LVCMOS to Differential LVECL Translator The MC100EPT24 is a LVTTL/LVCMOS to differential LVECL translator. Because LVECL levels and LVTTL/LVCMOS levels are used, a –3.3V, +3.3V and ground are required. The small outline 8–lead SOIC package and the single gate of the EPT24 makes it ideal for those applications where space, performance, and low power are at a premium. The EPT24 is available in the 100E standard and is compatible with ECL 100K logic levels. • 350ps Typical Propagation Delay • Maximum Frequency > 1.0GHz • Differential ECL Outputs • Small Outline SOIC Package • PNP LVTTL Inputs for Minimal Loading • Flow Through Pinouts • Q Output will default HIGH with inputs open • ESD Protection: 4000 KV HBM, 200 V MM • Moisture Sensitivity Level 1, Indefinite Time Out of Drypack. For Additional Information, See Application Note AND8003/D • Flammability Rating: UL–94 code V–0 @ 1/8”, Oxygen Index 28 to 34 • Transistor Count = 181 devices 1 2 3 45 6 7 8 Q GND VCC Figure 1. 8–Lead Pinout (Top View) and Logic Diagram D Q NC NC VEE LVTTL LVECL PIN DESCRIPTION PIN Q, Q D LVTTL Input FUNCTION Differential LVECL Outputs http://onsemi.com VCC GND Ground Positive Supply VEE Negative Supply Device Package Shipping ORDERING INFORMATION MC100EPT24D SOIC 98 Units/Rail MC100EPT24DR2 SOIC 2500 Tape & Reel SO–8 D SUFFIX CASE 751 MARKING DIAGRAM KPT24 1 8 1 8 A = Assembly Location L = Wafer Lot Y = Year W = Work Week ALYW *For additional information, see Application Note AND8002/D |
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