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ISL95810WIU8Z-T Datasheet(PDF) 11 Page - Intersil Corporation |
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ISL95810WIU8Z-T Datasheet(HTML) 11 Page - Intersil Corporation |
11 / 13 page 11 FN8090.1 October 7, 2005 Write Operation A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL95810 responds with an ACK. At this time, if the Data Byte is to be written only to volatile registers, then the device enters its standby state. If the Data Byte is to be written also to non-volatile memory, the ISL95810 begins its internal write cycle to non-volatile memory. During the internal non- volatile write cycle, the device ignores transitions at the SDA and SCL pins, and the SDA output is at a high impedance state. When the internal non-volatile write cycle is completed, the ISL95810 enters its standby state (See Figure 17). The byte at address 02h determines if the Data Byte is to be written to volatile and/or non-volatile memory (See “Memory Description” on page 7). Data Protection The WP pin has to be at logic HIGH to perform any Write operation to the device. When the WP is active (LOW) the device ignores Data Bytes of a Write Operation, does not respond to the Data Bytes with an ACK, and instead, goes to its standby state waiting for a new START condition. A STOP condition also acts as a protection of non-volatile memory. A valid Identification Byte, Address Byte, and total number of SCL pulses act as a protection of both volatile and non-volatile registers. During a Write sequence, the Data Byte is loaded into an internal shift register as it is received. If the Address Byte is 0 or 2, the Data Byte is transferred to the Wiper Register (WR) or to the Access Control Register respectively, at the falling edge of the SCL pulse that loads the last bit (LSB) of the Data Byte. If the Address Byte is 0, and the Access Control Register is all zeros (default), then the STOP condition initiates the internal write cycle to non-volatile memory. Read Operation A Read operation consist of a three byte instruction followed by one or more Data Bytes (See Figure 18). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W bit set to “0”, an Address Byte, a second START, and a second Identification byte with the R/W bit set to “1”. After each of the three bytes, the ISL95810 responds with an ACK. Then the ISL95810 then transmits the Data Byte. The master then terminates the read operation (issuing a STOP condition) following the last bit of the Data Byte (See Figure 18). The byte at address 02h determines if the Data Bytes being read are from volatile or non-volatile memory (See “Memory Description” on page 9.) FIGURE 18. READ SEQUENCE SIGNALS FROM THE MASTER SIGNALS FROM THE SLAVE SIGNAL AT SDA S T A R T IDENTIFICATION BYTE WITH R/W=0 ADDRESS BYTE A C K A C K 00 0 11 S T O P A C K 0 1 0 11 IDENTIFICATION BYTE WITH R/W=1 A C K S T A R T LAST READ DATA BYTE FIRST READ DATA BYTE A C K 000 0 00 0 0 0 000 ISL95810 |
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