REV. 0.0 Jan. 2002

M390S2858DT1

PC133 Registered DIMM

Parameter

Symbol

-7C

-7A

Unit

Note

Min

Max

Min

Max

CLK cycle time

CAS latency=3

7.5

1000

7.5

1000

ns

1

CAS latency=2

7.5

10

CLK to valid

output delay

CAS latency=3

5.4

5.4

ns

1,2

CAS latency=2

5.4

6

Output data

hold time

CAS latency=3

3

3

ns

2

CAS latency=2

3

3

CLK high pulse width

2.5

2.5

ns

3

CLK low pulse width

2.5

2.5

ns

3

Input setup time

1.5

1.5

ns

3

Input hold time

0.8

0.8

ns

3

CLK to output in Low-Z

1

1

ns

2

CLK to output

in Hi-Z

CAS latency=3

5.4

5.4

ns

CAS latency=2

5.4

6

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

Notes :

REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.