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IDT5T2110NLI Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT5T2110NLI Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 23 page  1 INDUSTRIALTEMPERATURERANGE IDT5T2110 2.5VZERODELAYPLLDIFFERENTIALCLOCKDRIVER TERACLOCK REF0 REF0/ VREF0 FB FB/ VREF2 RxS REF1 REF1/ VREF1 1 Q 1 Q 2 Q 2 Q 3 Q 3 Q 4 Q 4 Q PLL 5 Q 5 Q QFB QFB PD FS LOCK PE PLL_EN 0 1 /N DS1:0 3 3 REF_SEL 0 1 Divide Select 1F2:1 Divide Select 2F2:1 Divide Select 3F2:1 Divide Select 4F2:1 Divide Select 5F2:1 TxS Divide Select FBF2:1 OMODE PLL 1sOE 2sOE 3sOE 4sOE 5sOE MAY 2003 2004 Integrated Device Technology, Inc. DSC 5982/25 c INDUSTRIAL TEMPERATURE RANGE The IDT logo is a registered trademark of Integrated Device Technology, Inc. FEATURES: • 2.5VDD • 6 differential outputs • Low skew: 100ps all outputs • Selectable positive or negative edge synchronization • Tolerant of spread spectrum input clock • Synchronous output enable • Selectable inputs • Input frequency: 4.17MHz to 250MHz • Output frequency: 12.5MHz to 250MHz • 1.8V / 2.5V LVTTL: up to 250MHz • HSTL / eHSTL: up to 250MHz • Hot insertable and over-voltage tolerant inputs • 3-level inputs for selectable interface • 3-level inputs for feedback divide selection with multiply ratios of(1-6, 8, 10, 12) • Selectable HSTL, eHSTL, 1.8V/2.5V LVTTL, or LVEPECL input interface • Selectable differential or single-ended inputs and six differen- tial outputs • PLL bypass for DC testing • External differential feedback, internal loop filter • Low Jitter: <75ps cycle-to-cycle • Power-down mode • Lock indicator • Available in BGA and VFQFPN package FUNCTIONAL BLOCK DIAGRAM IDT5T2110 2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK™ DESCRIPTION: The IDT5T2110 is a 2.5V PLL differential clock driver intended for high performance computing and data-communications applications. The IDT5T2110 has six differential outputs in six banks, including a dedicated differential feedback. The redundant input capability allows for a smooth change over to a secondary clock source when the primary clock source is absent. The feedback bank allows divide-by-functionality from 1 to 12 through the use of the DS[1:0] inputs. This provides the user with frequency multiplication1to12withoutusingdividedoutputsforfeedback. Eachoutput bank also allows for a divide-by functionality of 2 or 4. The5T2110featuresauser-selectable,single-endedordifferentialinputto sixdifferentialoutputs. Thedifferentialclockdriveralsoactsasatranslatorfrom a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL, or 1.8V/2.5V LVTTL outputs. Selectableinterfaceiscontrolledby3-levelinputsignalsthatmaybehard-wired toappropriatehigh-mid-lowlevels. Thedifferentialoutputscanbesynchro- nouslyenabled/disabled. Furthermore, when PE is held high, all the outputs are synchronized with thepositiveedgeoftheREFclockinput.WhenPEisheldlow,alltheoutputs are synchronized with the negative edge of REF. |
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