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CY7C09269A
CY7C09369A
Document #: 38-06050 Rev. *A
Page 7 of 17
Notes:
9.
Test conditions used are Load 2.
10. This parameter is guaranteed by design, but it is not production tested.
Switching Characteristics Over the Operating Range
Parameter
Description
CY7C09269A
CY7C09369A
Unit
-6[1]
-7
-9
-12
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
fMAX1
fMax Flow-Through
53
45
40
33
MHz
fMAX2
fMax Pipelined
100
83
67
50
MHz
tCYC1
Clock Cycle Time - Flow-Through
19
22
25
30
ns
tCYC2
Clock Cycle Time - Pipelined
10
12
15
20
ns
tCH1
Clock HIGH Time - Flow-Through
6.5
7.5
12
12
ns
tCL1
Clock LOW Time - Flow-Through
6.5
7.5
12
12
ns
tCH2
Clock HIGH Time - Pipelined
4568
ns
tCL2
Clock LOW Time - Pipelined
4568
ns
tR
Clock Rise Time
3333
ns
tF
Clock Fall Time
3333
ns
tSA
Address Set-Up Time
3.5
4
4
4
ns
tHA
Address Hold Time
0011
ns
tSC
Chip Enable Set-Up Time
3.5
4
4
4
ns
tHC
Chip Enable Hold Time
0011
ns
tSW
R/W Set-Up Time
3.5
4
4
4
ns
tHW
R/W Hold Time
0011
ns
tSD
Input Data Set-Up Time
3.5
4
4
4
ns
tHD
Input Data Hold Time
0011
ns
tSAD
ADS Set-Up Time
3.5
4
4
4
ns
tHAD
ADS Hold Time
0011
ns
tSCN
CNTEN Set-Up Time
3.5
444
ns
tHCN
CNTEN Hold Time
0011
ns
tSRST
CNTRST Set-Up Time
3.5
4
4
4
ns
tHRST
CNTRST Hold Time
0011
ns
tOE
Output Enable to Data Valid
8
9
10
12
ns
tOLZ
[9, 10]
OE to Low Z
2222
ns
tOZ
[9, 10]
OE to High Z
17171717
ns
tCD1
Clock to Data Valid - Flow-Through
15
18
20
25
ns
tCD2
Clock to Data Valid - Pipelined
6.5
7.5
9
12
ns
tDC
Data Output Hold After Clock HIGH
2222
ns
tCKHZ
[9, 10]
Clock HIGH to Output High Z
29292929
ns
tCKLZ
[9, 10]
Clock HIGH to Output Low Z
2222
ns
Port to Port Delays
tCWDD
Write Port Clock HIGH to Read Data Delay
30
35
40
40
ns
tCCS
Clock to Clock Set-Up Time
9
10
15
15
ns
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