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CY7C1310BV18
CY7C1910BV18
CY7C1312BV18
CY7C1314BV18
Document #: 38-05619 Rev. *D
Page 2 of 25
Logic Block Diagram (CY7C1310BV18)
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
D[7:0]
Read Data Reg.
RPS
WPS
Q[7:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
8
20
8
16
8
NWS[1:0]
VREF
8
A(19:0)
20
C
C
8
Write
Reg
Write
Reg
CQ
CQ
8
DOFF
Logic Block Diagram (CY7C1910BV18)
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
D[8:0]
Read Data Reg.
RPS
WPS
Q[8:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
9
20
9
18
9
BWS[0]
VREF
9
A(19:0)
20
C
C
9
Write
Reg
Write
Reg
CQ
CQ
9
DOFF
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