SyncMOS Technologies Inc.

SM89S16R1

8-Bits Micro-controller

With 64KB Flash ROM & IKB RAM & RTC & ADC & PWM & PDWU embedded

Specifications subject to change without notice contact your sales representatives for the most recent information.

SM89S16R1 V1.0 JANUARY 2005

20

Internal Data memory

The data memory of SM89S16R1 consists of 1024 bytes internal data memory (256 bytes standard RAM and 768

bytes AUX-RAM). The AUX-RAM is enable by SCONF.1 ($BF.1), and read/write by MOVX

Analog to Digital Converter (ADC)

The ADC block diagram was shown as below:

Those are only 4 pins mirror to Port 2[7:4] at Vin<3:0>. The digital output DATA [11:4] were put into ADCD ($8FH).

And the ADC interrupt vector is 4BH.

The ADC SFR shown as below:

ADSCR ($8EH)

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Com

Con

ADCSS1

ADCSS0

CH1

CH0

COM: Read only. When conversion complete, it will be set.

CON: when set, the ADC will conversion continuous, else it will conversion only once.

ADCSS [1:0]: ADC clock select. (ADC_CLK range 500 KHz~2.5 MHz).If over frequency of ADC_CLK, the

conversion data may be unstable.

ADCSS1

ADCSS0

ADC_CLK

0

0

FOSC/8

0

1

FOSC/16

1

0

FOSC/32

1

1

FOSC/64

CH [1:0]: ADC channel select.

CH1

CH0

Input select

0

0

CH0

0

1

CH1

1

0

CH2

1

1

CH3

ADCD ($8FH)

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

AD.5

AD.4

AD.3

AD.2

AD.1

AD.0

*Read Only.

6-bit S A R A D C

VS S

VDD(= V re f)

A D C_ CL K

4

V A IN < 3 :0 > { P 2 .4 ~ P 2.7}

CH < 2 :0 > { A D S CR[3 :2 ]}

3

6

D A T A <5 :0 >

{ A D C D [7:2]}

A D C SS1 A D C SS 0 A D C _ C L K

0

0

F o sc /4

0

1

F o sc /8

1

0

F o sc /1 6

1

1

F o sc /3 2

A D C S S [1:0]= {A D S C R [5:4]}

C ontinuou s { A D S C R .6}

Co m p le te

{ A D S CR.7 }

Figure 16 ADC Block Diagram