LNBEH21

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read mode. The read mode is Master activated by sending the chip address with R/W bit set to 1. At the

following master generated clocks bits, the LNBEH21 issues a byte on the SDA data bus line (MSB

transmitted first).

At the ninth clock bit the MCU master can:

- acknowledge the reception, starting in this way the transmission of another byte from the LNBEH21;

- no acknowledge, stopping the read mode communication.

While the whole register is read back by the µP, only the two read-only bits OLF and OTF convey

diagnostic informations about the LNBEH21

Values are typical unless otherwise specified

the System Register (SR) is initialized to all zeroes, thus keeping the power blocks disabled. Once the

µP. This is due to 500mV of hysteresis provided in the UVL threshold to avoid false retriggering of the

Power-On reset circuit.

ADDRESS PIN

4 different addresses simply setting this pin at 4 fixed voltage levels (see table on page 11).

COMMUNICATION MODE SELECTION

VSEL pin (#14) operation are switched between two different functions:

- The TEN/VSEL pin controls the 22KHz bursting code, by enabling the internal 22KHz tone generator, to

PCL

TTX

OM

LLC

VOM

EN

OTF

OLF

Function

These bits are read exactly the same as

they were left after last write operation

0

1

0

1