Electronic Components Datasheet Search |
|
LNBEH21PD-TR Datasheet(PDF) 8 Page - STMicroelectronics |
|
LNBEH21PD-TR Datasheet(HTML) 8 Page - STMicroelectronics |
8 / 22 page LNBEH21 8/22 RECEIVED DATA (I2C bus READ MODE) The LNBEH21 can provide to the Master a copy of the SYSTEM REGISTER information via I2C bus in read mode. The read mode is Master activated by sending the chip address with R/W bit set to 1. At the following master generated clocks bits, the LNBEH21 issues a byte on the SDA data bus line (MSB transmitted first). At the ninth clock bit the MCU master can: - acknowledge the reception, starting in this way the transmission of another byte from the LNBEH21; - no acknowledge, stopping the read mode communication. While the whole register is read back by the µP, only the two read-only bits OLF and OTF convey diagnostic informations about the LNBEH21 Values are typical unless otherwise specified POWER-ON I2C INTERFACE RESET The I2C interface built in the LNBEH21 is automatically reset at power-on. As long as the VCC stays below the UnderVoltage Lockout threshold (6.7V typ.), the interface will not respond to any I2C command and the System Register (SR) is initialized to all zeroes, thus keeping the power blocks disabled. Once the VCC rises above 7.3V typ, the I 2C interface becomes operative and the SR can be configured by the main µP. This is due to 500mV of hysteresis provided in the UVL threshold to avoid false retriggering of the Power-On reset circuit. ADDRESS PIN Connecting this pin to GND the Chip I2C interface address is 0001000, but, it is possible to choice among 4 different addresses simply setting this pin at 4 fixed voltage levels (see table on page 11). COMMUNICATION MODE SELECTION I2C OM bit (Operating Mode selection bit) The LNBEH21 can work either in DiSEqCTM mode or in 13/18V Control Word mode; the selection of the communication mode is achieved through the dedicated I2C OM bit that must be respectively set to LOW or to HIGH. Depending on the communication mode selection (OM bit state) the I2C VOM bit and the TEN/ VSEL pin (#14) operation are switched between two different functions: VOM bit and TEN/VSEL pin functions with OM=0 (DiSEqCTM mode). - The TEN/VSEL pin controls the 22KHz bursting code, by enabling the internal 22KHz tone generator, to allow immediate DiSEqCTM data encoding. - In DiSEqCTM mode, the VOM I2C bit controls simultaneously the post-regulator output voltage (VOUT) and the DC/DC converter output voltage (VUP). The VOM bit function is to select the LNB output voltage to 13.25V or 19.5V respectively if VOM=0 or VOM=1 (14.25V or 20.5V if LLC=1) and VUP is set to VOUT+2.2V typ., according to DiSEqC section in the Truth Table on page 11; PCL TTX OM LLC VOM EN OTF OLF Function These bits are read exactly the same as they were left after last write operation 0 TJ<135°C, normal operation 1 TJ>150°C, power block disabled 0 IOUT<IOMAX, normal operation 1 IOUT>IOMAX, overload protection triggered |
Similar Part No. - LNBEH21PD-TR |
|
Similar Description - LNBEH21PD-TR |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |