Clock Generator for Pentium
III Server and Workstation Applications
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07068 Rev. **
05/04/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
Page 4 of 14
http://www.cypress.com
PRELIMINARY
C9851
AC Parameters (VDDI = VDD = VDDR = VDDL = VDDM = VDDC = 3.3V
±5%, TA = 0°C to +70°C)
133 MHz Host
100 MHz Host
Symbol
Parameter
Min
Max
Min
Max
Units
Notes
TPeriod
CPU[(1:6), (1:6)#] period -
7.35
7.65
9.85
10.2
nS
1, 2
Tr / Tf
CPU[(1:6), (1:6)#] rise and fall times
175
450
175
450
pS
2, 3
TSKEW1
skew from any CPU pair to any CPU pair
-
150
-
150
pS
2, 4, 5
TSKEW2
skew from package to package
-
100
-
100
pS
2, 4, 5
TCCJ
CPU[(1:6), (1:6)#] Cycle to Cycle Jitter
-
150
-
150
pS
2, 4, 5
Vover
CPU[(1:6), (1:6)#] Overshoot
Voh+0.2
Voh+0.2
V
2,10
Vunder
CPU[(1:6), (1:6)#] Undershoot
-0.2
-0.2
V
2, 10
Vcrossover
CPU(1:6) to CPU(1:6)# crossover point
45%Voh
55%Voh
45%Voh
55%Voh
V
2, 4
Tduty
Duty Cycle
45
55
45
55
%
2, 4
TPeriod
3V(MREF, MREF_B) period
15.0
15.3
20.0
20.4
nS
4, 5
THIGH
3V(MREF, MREF_B) high time
5.25
-
7.5
-
nS
2, 6
TLOW
3V(MREF, MREF_B) low time
5.05
-
7.3
-
nS
2, 7
Tr / Tf
3V(MREF, MREF_B) rise and fall times
0.4
1.6
0.4
1.6
nS
2, 3
TSKEW
3VMREF to 3VMREF_B skew
-
250
-
250
pS
2, 4, 5, 11
TCCJ
3V(MREF, MREF_B) Cycle to Cycle Jitter
-
250
-
250
pS
2, 4, 5
Tduty
Duty Cycle
45
55
45
55
%
2, 4
TPeriod
3V66 period
15.0
16.0
15.0
15.2
nS
1, 2, 4
THIGH
3V66 high time
5.25
-
5.25
-
nS
2,6
TLOW
3V66 low time
5.05
-
5.05
-
nS
2, 7
Tr / Tf
3V66 rise and fall times
0.5
2.0
0.5
2.0
nS
2, 3
TCCJ
3V66 Cycle to Cycle Jitter
-
300
-
300
pS
2, 4, 5
Tduty
Duty Cycle
45
55
45
55
%
2, 4
TPeriod
REF period
69.8413
71.0
69.8413
71.0
nS
1, 2, 4
Tr / Tf
REF rise and fall times
1.0
4.0
1.0
4.0
nS
2, 3
TCCJ
REFCycle to Cycle Jitter
-
1000
-
1000
pS
2, 4
Tduty
Duty Cycle
45
55
45
55
%
2, 4
tpZL, tpZH
Output enable delay (all outputs)
1.0
10.0
1.0
10.0
nS
9
tpLZ, tpZH
Output disable delay (all outputs)
1.0
10.0
1.0
10.0
nS
9
tstable
All clock Stabilization from power-up
3
3
mS
Group Limits and Parameters (applicable to all settings: Sel133/100# = x) continued
Note 1:
This parameter is measured at the crossing points of the differential signals, and acquired as an average over 1uS duration, with a crystal
center frequency of 14.31818MHz
Note 2:
All outputs loaded as per table 2 below.
Note 3:
Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and at 20% and 80% for
CPU[(1:6), (1:6)#] signals. (see Figs.7A & 7B)
Note 4:
Probes are placed on the pins, and measurements are acquired at 1.5V for 3.3V signals and at crossing points for CPU clocks (see Figs.7A
& 7B).
Note 5:
This measurement is applicable with Spread ON or Spread OFF.
Note 6:
Probes are placed on the pins, and measurements are acquired at 2.4V (see Figs. 7A & 7B)
Note 7:
Probes are placed on the pins, and measurements are acquired at 0.4V. (see Figs. 7A & 7B)
Note 9:
As this function is available through SEL(A,B), therefore, the time specified is guaranteed by design.
Note 10: Determined as a fraction of 2*(Trp-Trn) / (Trp+Trn) where Trp is a rising edge and Trn is an intersecting falling edge.
Note 11: 3VMref and 3VMref_b are 180 degrees out of phase, therefore, the skew is measured between the rising edge of one and the falling edge
of the other.
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