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LXT974BHC Datasheet(PDF) 11 Page - Intel Corporation |
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LXT974BHC Datasheet(HTML) 11 Page - Intel Corporation |
11 / 74 page Fast Ethernet 10/100 Quad Transceivers — LXT974/LXT975 Datasheet 11 Table 1. LXT974 Signal Detect/TP Select Signal Descriptions Pin#2 Symbol Type1 Signal Description 158 149 139 130 SD0/TP0 SD1/TP1 SD2/TP2 SD3/TP3 I Signal Detect - Ports 0 - 3. When SD/TPn pins are tied High or to a 5V PECL input, bit 19.2 = 1 and the operating mode of each respective port is forced to FX mode. In this mode, full-duplex is set via pin 117 (FDE_FX). When not using FX mode, SD/TPn pins should be tied to GNDT. TP Select - Ports 0 - 3. When SD/TPn pins are tied Low, bit 19.2 = 0. The operating mode of each port can be set to 10BASE-T, 100BASE-TX, or 100BASE-FX via the hardware control interface pins as shown in Table 8 on page 16. Note: Hardware control interface pins (CFG_0, CFG_1, CFG_2, FDE, BYPSCR, and AUTOENA) are global and set all ports simultaneously. In TP mode, network pins operate as described in Table 2. In FX mode, network pins are re-mapped and operate as described in Table 3. 1. Type Column Coding: I = Input, O = Output. 2. When not using fiber mode, SD/TPn pins should be tied to GNDT. Table 2. LXT974 Twisted-Pair Interface Signal Descriptions Pin# Symbol Type1 Signal Description 154, 157 145, 148 135, 138 126, 129 TPOP0, TPON0 TPOP1, TPON1 TPOP2, TPON2 TPOP3, TPON3 O Twisted-Pair Outputs, Positive & Negative - Ports 0-3. During 100BASE-TX or 10BASE-T operation, TPO pins drive 802.3 compliant pulses onto the line. 151, 152 142, 143 132, 133 123, 124 TPIP0, TPIN0 TPIP1, TPIN1 TPIP2, TPIN2 TPIP3, TPIN3 I Twisted-Pair Inputs, Positive & Negative - Ports 0-3. During 100BASE-TX or 10BASE-T operation, TPI pins receive differential 100BASE-TX or 10BASE-T signals from the line. 1. Type Column Coding: I = Input, O = Output. Table 3. LXT974 Fiber Interface Signal Descriptions Pin# Symbol Type1 Signal Description 154, 157 145, 148 135, 138 126, 129 FIBIN0, FIBIP0 FIBIN1, FIBIP1 FIBIN2, FIBIP2 FIBIN3, FIBIP3 I Fiber Inputs, Positive & Negative - Ports 0-3. During 100BASE-FX operation, FIBI pins receive differential PECL inputs from fiber transceivers. 151, 152 142, 143 132, 133 123, 124 FIBOP0, FIBON0 FIBOP1, FIBON1 FIBOP2, FIBON2 FIBOP3, FIBON3 O Fiber Outputs, Positive & Negative - Ports 0-3. During 100BASE-FX operation, FIBO pins produce differential PECL outputs for fiber transceivers. 1. Type Column Coding: I = Input, O = Output. |
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