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LM2502SM Datasheet(PDF) 5 Page - National Semiconductor (TI) |
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LM2502SM Datasheet(HTML) 5 Page - National Semiconductor (TI) |
5 / 27 page Pin Descriptions (Continued) Pin Name No. of Pins I/O, Type Description Master (SER) Slave (DES) POWER/GROUND PINS V DDA 1 Power Power Supply Pin for the MPL Interface. 2.9V to 3.3V V SSA 1 Ground Ground Pin for the MPL Interface, a low impedance ground path is required between the Master and the Slave device - see Applications Information section. V DDcore 1 Power Power Supply Pin for the digital core. 2.9V to 3.3V V SScore 1 Ground Ground Pin for the digital core. V DDIO 2 Power Power Supply Pin for the parallel interface. 1.7V to 3.3V V SSIO 2 Ground Ground Pin for the parallel interface. 9 NC Not Connected (C3-5, D3-5, E3-5). UFBGA Package only. 1 Ground DAP = Ground. LLP Package only. Note: I = Input, O = Output, IO = Input/Output, VDDIO ≤ VDD (VDDA =VDDcore). Do not float input pins. Master Pinout - UFBGA Package MST 12 34 56 7 A D0 D1 D2 V DDA INTR MD1 MC B D3 D4 D5 V SSA M/S* Mode MD0 C D6 D7 NC NC NC CS2* MF1 D V DDIO V SSIO NC NC NC V SScore V DDcore E D8 D9 NC NC NC CS1* PLLCON2 F D10 D11 D12 V SSIO MF0 PLLCON1 PD* G D13 D14 D15 V DDIO A/D PLLCON0 CLK Slave Pinout - UFBGA Package SLV 1 234 56 7 A D0 D1 D2 V DDA CLKDIS* MD0 MC B D3 D4 D5 V SSA M/S* Mode MD1 C D6 D7 NC NC NC CS2* MF1 D V DDIO V SSIO NC NC NC V SScore V DDcore E D8 D9 NC NC NC CS1* PLLCON2 F D10 D11 D12 V SSIO MF0 PLLCON1 PD* G D13 D14 D15 V DDIO A/D PLLCON0 CLK www.national.com 5 |
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